65k-neuron integrate-and-fire array transceiver with address-event reconfigurable synaptic routing. - Theodore Yu; Jongkil Park 001; Siddharth Joshi 001; Christoph Maier; Gert Cauwenberghs (BioCAS, 2012)

Event-driven neural integration and synchronicity in analog VLSI. - Theodore Yu; Jongkil Park 001; Siddharth Joshi 001; Christoph Maier; Gert Cauwenberghs (EMBC, 2012)

Live demonstration: Hierarchical Address-Event Routing architecture for reconfigurable large scale neuromorphic systems. - Jongkil Park 001; Theodore Yu; Christoph Maier; Siddharth Joshi 001; Gert Cauwenberghs (ISCAS, 2012)

A 12.6 mW 8.3 Mevents/s contrast detection 128×128 imager with 75 dB intra-scene DR asynchronous random-access digital readout. - Jongkil Park 001; Sohmyung Ha; Chul Kim; Siddharth Joshi 001; Theodore Yu; Wei Ma; Gert Cauwenberghs (BioCAS, 2014)

A 7.86 mW +12.5 dBm in-band IIP3 8-to-320 MHz capacitive harmonic rejection mixer in 65nm CMOS. - Chul Kim; Sohmyung Ha; Chris M. Thomas; Siddharth Joshi 001; Jongkil Park 001; Lawrence E. Larson; Gert Cauwenberghs (ESSCIRC, 2014)

Energy-recycling integrated 6.78-Mbps data 6.3-mW power telemetry over a single 13.56-MHz inductive link. - Sohmyung Ha; Chul Kim; Jongkil Park 001; Siddharth Joshi 001; Gert Cauwenberghs (VLSIC, 2014)

A CMOS 4-channel MIMO baseband receiver with 65dB harmonic rejection over 48MHz and 50dB spatial signal separation over 3MHz at 1.3mW. - Chul Kim; Siddharth Joshi 001; Chris M. Thomas; Sohmyung Ha; Abraham Akinin; Lawrence E. Larson; Gert Cauwenberghs (VLSIC, 2015)

Unsupervised Learning in Synaptic Sampling Machines. - Emre Neftci; Bruno U. Pedroni; Siddharth Joshi 001; Maruan Al-Shedivat; Gert Cauwenberghs (CoRR, 2015)

Forward table-based presynaptic event-triggered spike-timing-dependent plasticity. - Bruno U. Pedroni; Sadique Sheik; Siddharth Joshi 001; Georgios Detorakis; Somnath Paul; Charles Augustine; Emre Neftci; Gert Cauwenberghs (BioCAS, 2016)

A 6μW/MHz charge buffer with 7fF input capacitance in 65nm CMOS for non-contact electropotential sensing. - Siddharth Joshi 001; Chul Kim; Gert Cauwenberghs (ISCAS, 2016)

Neuromorphic architectures with electronic synapses. - Sukru Burc Eryilmaz; Siddharth Joshi 001; Emre Neftci; Weier Wan; Gert Cauwenberghs; H.-S. Philip Wong (ISQED, 2016)

Training a Probabilistic Graphical Model with Resistive Switching Electronic Synapses. - Sukru Burc Eryilmaz; Emre Neftci; Siddharth Joshi 001; SangBum Kim; Matthew BrightSky; Hsiang-Lan Lung; Chung Lam; Gert Cauwenberghs; H.-S. Philip Wong (CoRR, 2016)

Energy Recycling Telemetry IC With Simultaneous 11.5 mW Power and 6.78 Mb/s Backward Data Delivery Over a Single 13.56 MHz Inductive Link. - Sohmyung Ha; Chul Kim; Jongkil Park 001; Siddharth Joshi 001; Gert Cauwenberghs (IEEE J. Solid State Circuits, 2016)

A 1.3 mW 48 MHz 4 Channel MIMO Baseband Receiver With 65 dB Harmonic Rejection and 48.5 dB Spatial Signal Separation. - Chul Kim; Siddharth Joshi 001; Chris M. Thomas; Sohmyung Ha; Lawrence E. Larson; Gert Cauwenberghs (IEEE J. Solid State Circuits, 2016)

A 6.5-µW/MHz Charge Buffer With 7-fF Input Capacitance in 65-nm CMOS for Noncontact Electropotential Sensing. - Siddharth Joshi 001; Chul Kim; Gert Cauwenberghs (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Neuromorphic event-driven multi-scale synaptic connectivity and plasticity. - Siddharth Joshi 001; Bruno U. Pedroni; Gert Cauwenberghs (ACSSC, 2017)

From algorithms to devices: Enabling machine learning through ultra-low-power VLSI mixed-signal array processing. - Siddharth Joshi 001; Chul Kim; Sohmyung Ha; Gert Cauwenberghs (CICC, 2017)

Memristor for computing: Myth or reality? - Said Hamdioui; Shahar Kvatinsky; Gert Cauwenberghs; Lei Xie 005; Nimrod Wald; Siddharth Joshi 001; Hesham Mostafa Elsayed; Henk Corporaal; Koen Bertels (DATE, 2017)

21.7 2pJ/MAC 14b 8×8 linear transform mixed-signal spatial filter in 65nm CMOS with 84dB interference suppression. - Siddharth Joshi 001; Chul Kim; Sohmyung Ha; Yu Mike Chi; Gert Cauwenberghs (ISSCC, 2017)

Hierarchical Address Event Routing for Reconfigurable Large-Scale Neuromorphic Systems. - Jongkil Park 001; Theodore Yu; Siddharth Joshi 001; Christoph Maier; Gert Cauwenberghs (IEEE Trans. Neural Networks Learn. Syst., 2017)

High-Fidelity Spatial Signal Processing in Low-Power Mixed-Signal VLSI Arrays - Siddharth Joshi 001 (2017)

Unsupervised Synaptic Pruning Strategies for Restricted Boltzmann Machines. - Surabhi Kalyan; Siddharth Joshi 001; Sadique Sheik; Bruno U. Pedroni; Gert Cauwcnbcrghs (BioCAS, 2018)

A 92dB dynamic range sub-μVrms-noise 0.8μW/ch neural-recording ADC array with predictive digital autoranging. - Chul Kim; Siddharth Joshi 001; Hristos Courellis; Jun Wang 040; Cory T. Miller; Gert Cauwenberghs (ISSCC, 2018)

Sub-µVrms-Noise Sub-µW/Channel ADC-Direct Neural Recording With 200-mV/ms Transient Recovery Through Predictive Digital Autoranging. - Chul Kim; Siddharth Joshi 001; Hristos Courellis; Jun Wang 040; Cory T. Miller; Gert Cauwenberghs (IEEE J. Solid State Circuits, 2018)

DropOut and DropConnect for Reliable Neuromorphic Inference under Energy and Bandwidth Constraints in Network Connectivity. - Yasufumi Sakai; Bruno U. Pedroni; Siddharth Joshi 001; Abraham Akinin; Gert Cauwenberghs (AICAS, 2019)

Dropout and DropConnect for Reliable Neuromorphic Inference Under Communication Constraints in Network Connectivity. - Yasufumi Sakai; Bruno U. Pedroni; Siddharth Joshi 001; Satoshi Tanabe; Abraham Akinin; Gert Cauwenberghs (IEEE J. Emerg. Sel. Topics Circuits Syst., 2019)

Digitally Adaptive High-Fidelity Analog Array Signal Processing Resilient to Capacitive Multiplying DAC Inter-Stage Gain Error. - Siddharth Joshi 001; Chul Kim; Chris M. Thomas; Gert Cauwenberghs (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Device Non-Ideality Resilient Approach for Mapping Neural Networks to Crossbar Arrays. - Arman Kazemi; Cristobal Alessandri; Alan C. Seabaugh; Xiaobo Sharon Hu; Michael T. Niemier; Siddharth Joshi 001 (DAC, 2020)

A 1.52 pJ/Spike Reconfigurable Multimodal Integrate-and-Fire Neuron Array Transceiver. - Rajkumar Kubendran; Weier Wan; Siddharth Joshi 001; H.-S. Philip Wong; Gert Cauwenberghs (ICONS, 2020)

Quantizing Spiking Neural Networks with Integers. - Clemens J. S. Schaefer; Siddharth Joshi 001 (ICONS, 2020)

A 4.2-pJ/Conv 10-b Asynchronous ADC with Hybrid Two-Tier Level-Crossing Event Coding. - Rajkumar Kubendran; Jongkil Park 001; Ritvik Sharma; Chul Kim; Siddharth Joshi 001; Gert Cauwenberghs; Sohmyung Ha (ISCAS, 2020)

Memory Organization for Energy-Efficient Learning and Inference in Digital Neuromorphic Accelerators. - Clemens J. S. Schaefer; Patrick Faley; Emre O. Neftci; Siddharth Joshi 001 (ISCAS, 2020)

Embedding error correction into crossbars for reliable matrix vector multiplication using emerging devices. - Qiuwen Lou; Tianqi Gao; Patrick Faley; Michael T. Niemier; Xiaobo Sharon Hu; Siddharth Joshi 001 (ISLPED, 2020)

33.1 A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models. - Weier Wan; Rajkumar Kubendran; Sukru Burc Eryilmaz; Wenqiang Zhang; Yan Liao; Dabin Wu; Stephen R. Deiss; Bin Gao 006; Priyanka Raina; Siddharth Joshi 001; Huaqiang Wu; Gert Cauwenberghs; et al. (ISSCC, 2020)

Analog vs. Digital Spatial Transforms: A Throughput, Power, and Area Comparison. - Zephan M. Enciso; Seyed Hadi Mirfarshbafan; Oscar Castañeda; Clemens J. S. Schaefer; Christoph Studer; Siddharth Joshi 001 (MWSCAS, 2020)

Memory Organization and Structures for On-Chip Learning in Spiking Neural Networks. - Clemens J. S. Schaefer; Siddharth Joshi 001 (MWSCAS, 2020)

LSTMs for Keyword Spotting with ReRAM-Based Compute-In-Memory Architectures. - Clemens J. S. Schaefer; Mark Horeni; Pooria Taheri; Siddharth Joshi 001 (ISCAS, 2021)

Edge AI without Compromise: Efficient, Versatile and Accurate Neurocomputing in Resistive Random-Access Memory. - Weier Wan; Rajkumar Kubendran; Clemens J. S. Schaefer; Sukru Burc Eryilmaz; Wenqiang Zhang; Dabin Wu; Stephen R. Deiss; Priyanka Raina; He Qian; Bin Gao 006; Siddharth Joshi 001; Huaqiang Wu; et al. (CoRR, 2021)

Ruby: Improving Hardware Efficiency for Tensor Algebra Accelerators Through Imperfect Factorization. - Mark Horeni; Pooria Taheri; Po-An Tsai; Angshuman Parashar; Joel S. Emer; Siddharth Joshi 001 (ISPASS, 2022)

A compute-in-memory chip based on resistive random-access memory. - Weier Wan; Rajkumar Kubendran; Clemens J. S. Schaefer; Sukru Burc Eryilmaz; Wenqiang Zhang; Dabin Wu; Stephen R. Deiss; Priyanka Raina; He Qian; Bin Gao 006; Siddharth Joshi 001; Huaqiang Wu; et al. (Nat., 2022)

Mixed Precision Post Training Quantization of Neural Networks with Sensitivity Guided Search. - Clemens JS Schaefer; Elfie Guo; Caitlin Stanton; Xiaofan Zhang 001; Tom Jablin; Navid Lambert-Shirzad; Jian Li; Chiachen Chou; Siddharth Joshi 001; Yu Emma Wang (CoRR, 2023)

NeuroBench: Advancing Neuromorphic Computing through Collaborative, Fair and Representative Benchmarking. - Jason Yik; Soikat Hasan Ahmed; Zergham Ahmed; Brian Anderson; Andreas G. Andreou; Chiara Bartolozzi; Arindam Basu; Douwe den Blanken; Petrut Bogdan; Sander M. Bohté; Younes Bouhadjar; Sonia M. Buckley; et al. (CoRR, 2023)

Augmenting Hessians with Inter-Layer Dependencies for Mixed-Precision Post-Training Quantization. - Clemens JS Schaefer; Navid Lambert-Shirzad; Xiaofan Zhang 001; Chiachen Chou; Tom Jablin; Jian Li; Elfie Guo; Caitlin Stanton; Siddharth Joshi 001; Yu Emma Wang (CoRR, 2023)

Hadamard Domain Training with Integers for Class Incremental Quantized Learning. - Martin Schiemer; Clemens JS Schaefer; Jayden Parker Vap; Mark James Horeni; Yu Emma Wang; Juan Ye; Siddharth Joshi 001 (CoRR, 2023)

Improvements in Interlayer Pipelining of CNN Accelerators Using Genetic Algorithms. - Mark Horeni; Siddharth Joshi 001 (CoRR, 2023)

The Hardware Impact of Quantization and Pruning for Weights in Spiking Neural Networks. - Clemens JS Schaefer; Pooria Taheri; Mark Horeni; Siddharth Joshi 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Micro/Nano Circuits and Systems Design and Design Automation: Challenges and Opportunities. - Gert Cauwenberghs; Jason Cong; X. Sharon Hu; Siddharth Joshi 001; Subhasish Mitra; Wolfgang Porod; H.-S. Philip Wong (Proc. IEEE, 2023)

Hadamard Domain Training with Integers for Class Incremental Quantized Learning. - Martin Schiemer; Clemens JS Schaefer; Mark James Horeni; Yu Emma Wang; Juan Ye; Siddharth Joshi 001 (CoLLAs, 2024)

Estimating Post-Synaptic Effects for Online Training of Feed-Forward SNNs. - Thomas M. Summe; Clemens JS Schaefer; Siddharth Joshi 001 (ICONS, 2024)

Edge Inference with Fully Differentiable Quantized Mixed Precision Neural Networks. - Clemens J. S. Schaefer; Siddharth Joshi 001; Shan Li; Raúl Blázquez (WACV, 2024)

Slax: A Composable JAX Library for Rapid and Flexible Prototyping of Spiking Neural Networks. - Thomas Summe; Siddharth Joshi 001 (CoRR, 2024)

A Remedy to Compute-in-Memory with Dynamic Random Access Memory: 1FeFET-1C Technology for Neuro-Symbolic AI. - Xunzhao Yin; Hamza Errahmouni Barkam; Franz Müller 001; Yu Jiang 001; Mohsen Imani; Sukhrob Abdulazhanov; Alptekin Vardar; Nellie Laleni; Zijian Zhao 001; Jiahui Duan; Zhiguo Shi 001; Siddharth Joshi 001; et al. (CoRR, 2024)

Hadamard-Walsh Channelized Receivers: Theory, Implementation, and Applications. - Adyant Balaji; Zhaoyi Liu; Siddharth Joshi 001; Gert Cauwenberghs (ISCAS, 2025)

Huff-LLM: End-to-End Lossless Compression for Efficient LLM Inference. - Patrick Yubeaton; Tareq Mahmoud; Shehab Naga; Pooria Taheri; Tianhua Xia; Arun George; Yasmein Khalil; Sai Qian Zhang; Siddharth Joshi 001; Chinmay Hegde; Siddharth Garg (CoRR, 2025)

An In-Situ Spatial-Temporal Sequence Detector for Neuromorphic Vision Sensor Empowered by High Density Vertical NAND Storage. - Zijian Zhao 001; Varun Darshana Parekh; Po-Kai Hsu; Yixin Qin; Yiming Song; A. N. M. Nafiul Islam; Ningyuan Cao; Siddharth Joshi 001; Thomas Kämpfe; Moonyoung Jung; Kwangyou Seo; Kwangsoo Kim; et al. (CoRR, 2025)