Design of Low Power 5-Bit Hybrid Flash ADC. - S. M. Mayur; Siddharth R. K.; Kumar Y. B. Nithin; M. H. Vasantha (ISVLSI, 2016)

Design of 5-Bit Flash ADC Using Multiple Input Standard Cell Gates for Large Input Swing. - Sumit Khalapure; Siddharth R. K.; Kumar Y. B. Nithin; M. H. Vasantha (ISVLSI, 2017)

Design of Low Power 4-Bit 400MS/s Standard Cell Based Flash ADC. - S. M. Mayur; Siddharth R. K.; Kumar Y. B. Nithin; M. H. Vasantha (ISVLSI, 2017)

A Low-Power Auxiliary Circuit for Level-Crossing ADCs in IoT-Sensor Applications. - Siddharth R. K.; Kumar Y. B. Nithin; M. H. Vasantha; Edoardo Bonizzoni (ISCAS, 2018)

Design of Area-Power-Delay Efficient Square Root Carry Select Adder. - Chetan Kamble; Siddharth R. K.; Shivnarayan Patidar; M. H. Vasantha; Nithin Y. B. Kumar (iSES, 2018)

An Asynchronous Analog to Digital Converter for Surveillance Camera Applications. - Siddharth R. K.; Sunil R.; Nithin Y. B. Kumar; M. H. Vasantha; Edoardo Bonizzoni (ISVLSI, 2018)

Two-Step Flash ADC Using Standard Cell Based Flash ADCs. - Rahul E.; Siddharth R. K.; Vivek Sharma 002; M. H. Vasantha; Nithin Kumar Yernad Balachandra (iSES, 2019)

Process Corner Calibration for Standard Cell Based Flash ADC. - Pradeep R.; Siddharth R. K.; Nithin Kumar Yernad Balachandra; Vasantha Moodabettu Harishchandra (iSES, 2019)

An Asynchronous Analog to Digital Converter for Video Camera Applications. - Sunil R.; Siddharth R. K.; Nithin Y. B. Kumar; M. H. Vasantha (ISVLSI, 2019)

A 1 V, 39 μ W, 5-bit Multi-Level Comparator based Flash ADC. - Nitish Kumar; Siddharth R. K.; Nithin Y. B. Kumar; M. H. Vasantha (iSES, 2020)

A 1.8 V Quadrature Phase LC Oscillator for 5G Applications. - Sanmitra Bharat Naik; Siddharth R. K.; Anirban Chatterjee; Nithin Kumar Y. B.; M. H. Vasantha; Ramnath Kini (iSES, 2020)

A 1.8 V, Mode-Configurable Hybrid Smart ADC. - Tejas J. Shahane; Siddharth R. K.; Kumar Y. B. Nithin; Vasantha M. H. (iSES, 2020)

A Novel Single Event Upset Tolerant 12T Memory Cell for Aerospace Applications. - Suraj Dohar; Siddharth R. K.; Vasantha M. H.; Nithin Kumar Y. B. (ISVLSI, 2020)

A Wideband 12 Phase Ring Oscillator for 5G Applications. - Sanmitra Bharat Naik; Siddharth R. K.; Anirban Chatterjee; Nithin Kumar Y. B.; Vasantha M. H.; Ramnath Kini (MWSCAS, 2020)

6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process. - Siddharth Rajkumar Kala; Sushma Chandaka; Nithin Kumar Yernad Balachandra; Vasantha Moodabettu Harishchandra; Edoardo Bonizzoni (IET Circuits Devices Syst., 2020)

Power Saving Scheme for Process Corner Calibrated Standard Cell Based Flash ADC in Wireless Surveillance Applications. - Siddharth R. K.; Nithin Y. B. Kumar; M. H. Vasantha (SN Comput. Sci., 2020)

A 1-V, 3-GHz Strong-Arm Latch Voltage Comparator for High Speed Applications. - Siddharth R. K.; Y. Jaya Satyanarayana; Nithin Y. B. Kumar; M. H. Vasantha; Edoardo Bonizzoni (IEEE Trans. Circuits Syst., 2020)

A 1-V, 5-Bit, 180-µW, Differential Pulse Position Modulation ADC in 65-nm CMOS Process. - Peta Guruprakashkumar; Siddharth R. K.; Nithin Kumar Y. B.; Vasantha M. H.; Edoardo Bonizzoni (ISCAS, 2021)

A 1-V, 10-bit, 250 MS/s, Current-Steering Segmented DAC for Video Applications. - Shiv Chandra Kumar; Siddharth R. K.; Nithin Kumar Y. B.; M. H. Vasantha (ISVLSI, 2021)

A 1 V Double-Balanced Mixer for 2.4-2.5 GHz ISM Band Applications. - Sanmitra Bharat Naik; Siddharth R. K.; Anirban Chatterjee; Kumar Y. B. Nithin; M. H. Vasantha; Ramnath Kini (VLSID, 2021)

A 11-ns, 3.85-fJ, Deep Sub-threshold, Energy Efficient Level Shifter in 65-nm CMOS. - R. D. Balaji; Siddharth R. K.; Sanmitra Bharat Naik; Y. B. Nithin Kumar; M. H. Vasantha; Edoardo Bonizzoni (ISCAS, 2023)

Approximate Three-Operand Binary Adder for Error-Resilient Applications. - Darshan Halliyavar; Siddharth R. K.; Vasantha M. H.; Nithin Kumar Y. B.; Sithara Raveendran (iSES, 2023)

A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process. - Rupesh D. Kadhao; Siddharth R. K.; Nithin Kumar Y. B.; Vasantha M. H.; Devesh Dwivedi (VLSID, 2023)

Partition Bound Random Number-Based Particle Swarm Optimization for Analog Circuit Sizing. - K. G. Shreeharsha; Siddharth R. K.; M. H. Vasantha; Y. B. Nithin Kumar (IEEE Access, 2023)

Power Reduction of a Level Triggered D Flip-Flop using Clock Gating and Power Gating Techniques. - Yamana Ashok Kumar; Nithin Kumar Y. B; Vasantha M. H.; Siddharth R. K. (iSES, 2024)

N-Parallel Paths-Based D-Latch for High-Speed Applications. - Rakhi R.; Siddharth R. K.; K. G. Shreeharsha; M. H. Vasantha; Nithin Kumar Yernad Balachandra (IEEE Access, 2024)

An Error Bound Particle Swarm Optimization for Analog Circuit Sizing. - K. G. Shreeharsha; Siddharth R. K.; M. H. Vasantha; Kumar Y. B. Nithin (IEEE Access, 2024)

A 0.9 V Configurable Dual Mode Comparator using a Supply Boosting Technique. - Sourabh Mestry; Siddharth R. K.; Nithin Kumar Y. B; Vasantha M. H.; Edoardo Bonizzoni (ISCAS, 2025)