Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems. - Manu Komalan; Sushil Sakhare; Trong Huynh Bao; Siddharth Rao; Woojin Kim; Christian Tenllado; José Ignacio Gómez; Gouri Sankar Kar; Arnaud Furnémont; Francky Catthoor (ISCAS, 2017)

Electrical Modeling of STT-MRAM Defects. - Lizhou Wu; Mottaqiallah Taouil; Siddharth Rao; Erik Jan Marinissen; Said Hamdioui (ITC, 2018)

Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing. - Lizhou Wu; Siddharth Rao; Guilherme Cardoso Medeiros; Mottaqiallah Taouil; Erik Jan Marinissen; Farrukh Yasin; Sebastien Couet; Said Hamdioui; Gouri Sankar Kar (ETS, 2019)

Device-Aware Test: A New Test Approach Towards DPPB Level. - Moritz Fieback; Lizhou Wu; Guilherme Cardoso Medeiros; Hassen Aziza; Siddharth Rao; Erik Jan Marinissen; Mottaqiallah Taouil; Said Hamdioui (ITC, 2019)

Impact of Magnetic Coupling and Density on STT-MRAM Performance. - Lizhou Wu; Siddharth Rao; Mottaqiallah Taouil; Erik Jan Marinissen; Gouri Sankar Kar; Said Hamdioui (DATE, 2020)

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs. - Lizhou Wu; Siddharth Rao; Mottaqiallah Taouil; Erik Jan Marinissen; Gouri Sankar Kar; Said Hamdioui (ITC, 2020)

Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests. - Lizhou Wu; Mottaqiallah Taouil; Siddharth Rao; Erik Jan Marinissen; Said Hamdioui (CoRR, 2020)

Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM. - Lizhou Wu; Siddharth Rao; Mottaqiallah Taouil; Erik Jan Marinissen; Gouri Sankar Kar; Said Hamdioui (DATE, 2021)

Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution. - Simon Van Beek; Siddharth Rao; Shreya Kundu; Woojin Kim; Barry J. O'Sullivan; Stefan Cosemans; Farrukh Yasin; Robert Carpenter; Sebastien Couet; Shamin H. Sharifi; Nico Jossart; Davide Crotti; et al. (IRPS, 2021)

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions. - Lizhou Wu; Siddharth Rao; Mottaqiallah Taouil; Erik Jan Marinissen; Gouri Sankar Kar; Said Hamdioui (ITC, 2021)

Defect and Fault Modeling Framework for STT-MRAM Testing. - Lizhou Wu; Siddharth Rao; Mottaqiallah Taouil; Guilherme Cardoso Medeiros; Moritz Fieback; Erik Jan Marinissen; Gouri Sankar Kar; Said Hamdioui (IEEE Trans. Emerg. Top. Comput., 2021)

MTJ degradation in SOT-MRAM by self-heating-induced diffusion. - Simon Van Beek; Kaiming Cai; Siddharth Rao; Ganesh Jayakumar; Sebastien Couet; Nico Jossart; Adrian Vaisman Chasin; Gouri Sankar Kar (IRPS, 2022)

Selective operations of multi-pillar SOT-MRAM for high density and low power embedded memories. - Kaiming Cai; Simon Van Beek; Siddharth Rao; K. Fan; M. Gupta; Van D. Nguyen; Ganesh Jayakumar; Giacomo Talmelli; S. Couet; Gouri Sankar Kar (VLSI Technology and Circuits, 2022)

Special Session: STT-MRAMs: Technology, Design and Test. - Anteneh Gebregiorgis; Lizhou Wu; Christopher Münch; Siddharth Rao; Mehdi B. Tahoori; Said Hamdioui (VTS, 2022)

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs. - Lizhou Wu; Siddharth Rao; Mottaqiallah Taouil; Erik Jan Marinissen; Gouri Sankar Kar; Said Hamdioui (IEEE Trans. Computers, 2022)

MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design. - Lizhou Wu; Siddharth Rao; Mottaqiallah Taouil; Erik Jan Marinissen; Gouri Sankar Kar; Said Hamdioui (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Device Aware Diagnosis for Unique Defects in STT-MRAMs. - Ahmed Aouichi; Sicong Yuan; Moritz Fieback; Siddharth Rao; Woojin Kim; Erik Jan Marinissen; Sebastien Couet; Mottaqiallah Taouil; Said Hamdioui (ATS, 2023)

Magnetic Domain Wall Memory: A DTCO study for Memory Applications. - M. Gupta; Siddharth Rao; Gouri Sankar Kar; S. Couet (ESSDERC, 2023)

Spin-orbit torque MRAM for ultrafast cache and neuromorphic computing applications. - Siddharth Rao; Kaiming Cai; Giacomo Talmelli; Nathali Franchina-Vergel; Ward Janssens; Hubert Hody; Farrukh Yasin; Kurt Wostyn; Sebastien Couet (IMW, 2023)

MTJ degradation in multi-pillar SOT-MRAM with selective writing. - Simon Van Beek; Kaiming Cai; Kaiquan Fan; Giacomo Talmelli; Anna Trovato; Nico Jossart; Siddharth Rao; Adrian Vaisman Chasin; Sebastien Couet (IRPS, 2023)

Hard Error Correction in STT-MRAM. - Surendra Hemaram; Mehdi B. Tahoori; Francky Catthoor; Siddharth Rao; Sebastien Couet; Gouri Sankar Kar (ASPDAC, 2024)

Design-for-Test for Intermittent Faults in STT-MRAMs. - Sicong Yuan; Mohammad Amin Yaldagard; Hanzhi Xun; Moritz Fieback; Erik Jan Marinissen; Woojin Kim; Siddharth Rao; Sebastien Couet; Mottaqiallah Taouil; Said Hamdioui (ETS, 2024)

Testing STT-MRAMs: Do We Need Magnets in our Automated Test Equipment? - Sicong Yuan; Hanzhi Xun; Woojin Kim; Siddharth Rao; Erik Jan Marinissen; Sebastien Couet; Moritz Fieback; Mottaqiallah Taouil; Said Hamdioui (ITC, 2024)

Soft and Hard Error-Correction Techniques in STT-MRAM. - Surendra Hemaram; Mehdi B. Tahoori; Francky Catthoor; Siddharth Rao; Sebastien Couet; Valerio Pica; Gouri Sankar Kar (IEEE Des. Test, 2024)

InterA-ECC: Interconnect-Aware Error Correction in STT-MRAM. - Surendra Hemaram; Mahta Mayahinia; Mehdi B. Tahoori; Francky Catthoor; Siddharth Rao; Sebastien Couet; Tommaso Marinelli; Anita Farokhnejad; Gouri Sankar Kar (DATE, 2025)