A methodology for power characterization of associative memories. - Dawei Li; Siddhartha Joshi; Seda Ogrenci Memik; James Hoff; Sergo Jindariani; Tiehui Liu 001; Jamieson Olsen; Nhan Tran (ICCD, 2015)

A content addressable memory with multi-Vdd scheme for low power tunable operation. - Siddhartha Joshi; Dawei Li; Seda Ogrenci Memik; Grzegorz Deptuch; James Hoff; Sergo Jindariani; Tiehui Liu 001; Jamieson Olsen; Nhan Tran (MWSCAS, 2017)

End-to-End Analysis of Integration for Thermocouple-Based Sensors Into 3-D ICs. - Dawei Li; Siddhartha Joshi; Ji-Hoon Kim; Seda Ogrenci Memik (IEEE Trans. Very Large Scale Integr. Syst., 2017)

MLParest: Machine Learning based Parasitic Estimation for Custom Circuit Design. - Brett Shook; Prateek Bhansali; Chandramouli V. Kashyap; Chirayu Amin; Siddhartha Joshi (DAC, 2020)

Dynamically Reconfigurable Data Readout of Pixel Detectors for Automatic Synchronization with Data Acquisition Systems. - Farah Fahim; Simone Bianconi; Jacob Rabinowitz; Siddhartha Joshi; Hooman Mohseni (Sensors, 2020)

A Low-Power, High-Speed Readout for Pixel Detectors Based on an Arbitration Tree. - Farah Fahim; Siddhartha Joshi; Seda Ogrenci-Memik; Hooman Mohseni (IEEE Trans. Very Large Scale Integr. Syst., 2020)