Analysis of Power Consumption Using a New Methodology for the Capacitance Modeling of Complex Logic Gates. - Sidinei Ghissoni; João Baptista dos Santos Martins; Ricardo Augusto da Luz Reis; José C. Monteiro 001 (PATMOS, 2009)

Radix-2 Decimation in Time (DIT) FFT implementation based on a Matrix-Multiple Constant multiplication approach. - Sidinei Ghissoni; Eduardo Costa 001; Cristiano Lazzari; José Monteiro 001; Levent Aksoy; Ricardo Reis 001 (ICECS, 2010)

Combination of constant matrix multiplication and gate-level approaches for area and power efficient hybrid radix-2 DIT FFT realization. - Sidinei Ghissoni; Eduardo Costa 001; José Monteiro 001; Ricardo Reis 001 (ICECS, 2011)

Efficient area and power multiplication part of FFT based on twiddle factor decomposition. - Sidinei Ghissoni; Eduardo Costa 001; José Monteiro 001; Ricardo Reis 001 (ICECS, 2012)

Reducing switching activity in FIR filters by reordering the coefficients through the use of improved heuristic algorithm. - João G. Nizer Rahmeier; Angelo G. da Luz; Eduardo A. C. da Costa; Sidinei Ghissoni (ICECS, 2013)

Reducing the Hamming distance of encoded FFT twiddle factors using improved heuristic algorithms. - Angelo Goncalves da Luz; Eduardo A. C. da Costa; Sidinei Ghissoni (LASCAS, 2013)

Implementation of power efficient multicore FFT datapaths by reordering the twiddle factors. - Sidinei Ghissoni; Eduardo A. C. da Costa; Angelo Goncalves da Luz (VLSI-SoC, 2014)

Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs. - Sidinei Ghissoni; Eduardo Costa 001; Ricardo Reis 001 (PATMOS, 2015)

Optimization of Single-Stage FFT Architectures Using Multiple Constant Multiplication. - João G. Nizer Rahmeier; Eduardo A. C. da Costa; Alessandro Girardi; Sidinei Ghissoni (SBCCI, 2018)