A model-first design and verification flow for analog-digital convergence systems: A high-speed receiver example in digital TVs. - Jaeha Kim; Sigang Ryu; Byoung-Joo Yoo; Hanseok Kim; Yunju Choi; Deog-Kyoon Jeong (ISCAS, 2012)

A 9.2 GHz Digital Phase-Locked Loop With Peaking-Free Transfer Function. - Sigang Ryu; Hwanseok Yeo; Yoontaek Lee; Seuk Son; Jaeha Kim (IEEE J. Solid State Circuits, 2014)

13.1 A 940MHz-bandwidth 28.8µs-period 8.9GHz chirp frequency synthesizer PLL in 65nm CMOS for X-band FMCW radar applications. - Hwanseok Yeo; Sigang Ryu; Yoontaek Lee; Seuk Son; Jaeha Kim (ISSCC, 2016)

A 2 × Blind Oversampling FSE Receiver With Combined Adaptive Equalization and Infinite-Range Timing Recovery. - Seuk Son; Sigang Ryu; Hwanseok Yeo; Jaeha Kim (IEEE J. Solid State Circuits, 2019)

An Accurate and Noise-Resilient Spread-Spectrum Clock Tracking Aid for Digitally-Controlled Clock and Data Recovery Loops. - Sigang Ryu; Seuk Son; Jaeha Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Time-Based Pipelined ADC Using Integrate-and-Fire Multiplying-DAC. - Sigang Ryu; Chan Young Park; Wooryeol Kim; Seuk Son; Jaeha Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

A Scalable Platform for Single-Snapshot Direction Of Arrival (DOA) Estimation in Massive MIMO Systems. - Adou Sangbone Assoa; Ashwin Bhat; Sigang Ryu; Arijit Raychowdhury (ACM Great Lakes Symposium on VLSI, 2023)

A 65nm 60mW Dual-Loop Adaptive Digital Beamformer with Optimized Sidelobe Cancellation and On-Chip DOA Estimation for mm-Wave Applications. - Sigang Ryu; Adou Sangbone Assoa; Shota Konno; Arijit Raychowdhury (VLSI Technology and Circuits, 2023)

30.1 A 40nm VLIW Edge Accelerator with 5MB of 0.256pJ/b RRAM and a Localization Solver for Bristle Robot Surveillance. - Samuel D. Spetalnick; Ashwin Sanjay Lele; Brian Crafton; Muya Chang; Sigang Ryu; Jong-Hyeok Yoon; Zhijian Hao; Azadeh Ansari; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (ISSCC, 2024)

A 65nm Delta-Sigma ADC Based VDD-Variation-Tolerant Power-Side-Channel-Attack Monitor with Detection Capability Down to 0.25Ω. - Shota Konno; Zachary J. Ellis; Anupam Golder; Sigang Ryu; Daniel Dinu; Avinash Varna 001; Sanu Mathew; Arijit Raychowdhury (VLSI Technology and Circuits, 2024)

Fractionally-Spaced Equalizers as Clock and Data Recovery Loops. - Sigang Ryu; Jaeha Kim; Arijit Raychowdhury (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An Edge Accelerator With 5 MB of 0.256-pJ/bit Embedded RRAM and a Localization Solver for Bristle Robot Surveillance. - Samuel D. Spetalnick; Ashwin Sanjay Lele; Brian Crafton; Muya Chang; Sigang Ryu; Jong-Hyeok Yoon; Zhijian Hao; Azadeh Ansari; Win-San Khwa; Yu-Der Chih; Meng-Fan Chang; Arijit Raychowdhury (IEEE J. Solid State Circuits, 2025)

MDS-DOA: Fusing Model-Based and Data-Driven Approaches for Modular, Distributed, and Scalable Direction-of-Arrival Estimation. - Adou Sangbone Assoa; Ashwin Bhat; Sigang Ryu; Arijit Raychowdhury (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)