Circuit Design Challenges in Computing-in-Memory for AI Edge Devices. - Xin Si; He Qian; Meng-Fan Chang; Cheng-Xin Xue; Jian-Wei Su; Zhixiao Zhang; Sih-Han Li; Shyh-Shyuan Sheu; Heng-Yuan Lee; Ping-Cheng Chen; Huaqiang Wu (ASICON, 2019)

A 55nm 1-to-8 bit Configurable 6T SRAM based Computing-in-Memory Unit-Macro for CNN-based AI Edge Processors. - Zhixiao Zhang; Jia-Jing Chen; Xin Si; Yung-Ning Tu; Jian-Wei Su; Wei-Hsing Huang; Jing-Hong Wang; Wei-Chen Wei; Yen-Cheng Chiu; Je-Min Hong; Shyh-Shyuan Sheu; Sih-Han Li; et al. (A-SSCC, 2019)

15.2 A 28nm 64Kb Inference-Training Two-Way Transpose Multibit 6T SRAM Compute-in-Memory Macro for AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Zhixiao Zhang; Hongwu Jiang; et al. (ISSCC, 2020)

A 4-Kb 1-to-8-bit Configurable 6T SRAM-Based Computation-in-Memory Unit-Macro for CNN-Based AI Edge Processors. - Yen-Cheng Chiu; Zhixiao Zhang; Jia-Jing Chen; Xin Si; Ruhui Liu; Yung-Ning Tu; Jian-Wei Su; Wei-Hsing Huang; Jing-Hong Wang; Wei-Chen Wei; Je-Min Hung; Shyh-Shyuan Sheu; et al. (IEEE J. Solid State Circuits, 2020)

A 1280 x 720 Micro-LED Display Driver with 10-Bit Current-Mode Pulse Width Modulation. - Pei-Yi Lai Lee; Ya-Wen Yang; Sih-Han Li; Jian-Jhih Sun; Tzu Yi Hung; Chih-Wen Lu; Yen-Hsiang Fang; Wei-Hung Kuo; Li-Chun Huang; Guo-Dung John Su; Poki Chen (A-SSCC, 2021)

A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration. - Chih-Sheng Lin; Fu-Cheng Tsai; Jian-Wei Su; Sih-Han Li; Tian-Sheuan Chang; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; Chih-I Wu; Tuo-Hung Hou (A-SSCC, 2021)

16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips. - Jian-Wei Su; Yen-Chi Chou; Ruhui Liu; Ta-Wei Liu; Pei-Jung Lu; Ping-Chun Wu; Yen-Lin Chung; Li-Yang Hung; Jin-Sheng Ren; Tianlong Pan; Sih-Han Li; Shih-Chieh Chang; et al. (ISSCC, 2021)

A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. - Ping-Chun Wu; Jian-Wei Su; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Fu-Chun Chang; Yuan Wu 009; Ho-Yu Chen; Chen-Hsun Lin; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; et al. (ISSCC, 2022)

An Embedded Multi-Die Active Bridge (EMAB) Chip for Rapid-Prototype Programmable 2.5D/3D Packaging Technology. - Jie Zhang; Wei Lu; Po-Tsang Huang; Sih-Han Li; Tsung-Yi Hung; Shih-Hsien Wu; Ming-Ji Dai; I-Shan Chung; Wen-Chao Chen; Chin-Hung Wang; Shyh-Shyuan Sheu; Hung-Ming Chen; et al. (VLSI Technology and Circuits, 2022)

Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips. - Jian-Wei Su; Xin Si; Yen-Chi Chou; Ting-Wei Chang; Wei-Hsing Huang; Yung-Ning Tu; Ruhui Liu; Pei-Jung Lu; Ta-Wei Liu; Jing-Hong Wang; Yen-Lin Chung; Jin-Sheng Ren; et al. (IEEE J. Solid State Circuits, 2022)

A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices. - Ping-Chun Wu; Jian-Wei Su; Li-Yang Hong; Jin-Sheng Ren; Chih-Han Chien; Ho-Yu Chen; Chao-En Ke; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; et al. (ISSCC, 2023)

A 8-b-Precision 6T SRAM Computing-in-Memory Macro Using Segmented-Bitline Charge-Sharing Scheme for AI Edge Chips. - Jian-Wei Su; Yen-Chi Chou; Ruhui Liu; Ta-Wei Liu; Pei-Jung Lu; Ping-Chun Wu; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Tianlong Pan; Chuan-Jia Jhang; Wei-Hsing Huang; et al. (IEEE J. Solid State Circuits, 2023)

Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-Based In-Memory Encryption Macro for Dynamic Edge Security. - Chih-Sheng Lin; Bo-Cheng Chiou; Yin-Jia Yang; Jian-Wei Su; Kuo-Hua Tseng; Yun-Ting Ho; Chih-Ming Lai; Sih-Han Li; Tian-Sheuan Chang; Shan-Ming Chang; Shyh-Shyuan Sheu; Wei-Chung Lo; et al. (VLSI Technology and Circuits, 2024)

Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology. - Wei Lu; Jie Zhang; Yi-Hui Wei; Hsu-Ming Hsiao; Sih-Han Li; Chao-Kai Hsu; Chih-Cheng Hsiao; Feng-Hsiang Lo; Shyh-Shyuan Sheu; Chin-Hung Wang; Wei-Chung Lo; Shih-Chieh Chang; et al. (VLSI Technology and Circuits, 2024)

A Floating-Point 6T SRAM In-Memory-Compute Macro Using Hybrid-Domain Structure for Advanced AI Edge Chips. - Ping-Chun Wu; Jian-Wei Su; Li-Yang Hong; Jin-Sheng Ren; Chih-Han Chien; Ho-Yu Chen; Chao-En Ke; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; Wei-Chung Lo; Shih-Chieh Chang; et al. (IEEE J. Solid State Circuits, 2024)

8-Bit Precision 6T SRAM Compute-in-Memory Macro Using Global Bitline-Combining Scheme for Edge AI Chips. - Jian-Wei Su; Pei-Jung Lu; Ping-Chun Wu; Yen-Chi Chou; Ta-Wei Liu; Yen-Lin Chung; Li-Yang Hung; Jin-Sheng Ren; Wei-Hsing Huang; Chih-Han Chien; Peng-I Mei; Sih-Han Li; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

An 8b-Precision 6T SRAM Computing-in-Memory Macro Using Time-Domain Incremental Accumulation for AI Edge Chips. - Ping-Chun Wu; Jian-Wei Su; Yen-Lin Chung; Li-Yang Hong; Jin-Sheng Ren; Fu-Chun Chang; Yuan Wu 009; Ho-Yu Chen; Chen-Hsun Lin; Hsu-Ming Hsiao; Sih-Han Li; Shyh-Shyuan Sheu; et al. (IEEE J. Solid State Circuits, 2024)