Siladitya Dey
Orcid: 0000-0002-2387-4670Affiliations:
- Oregon State University, School of Electrical Engineering and Computer Science, Corvallis, OR, USA
According to our database1,
Siladitya Dey
authored at least 11 papers
between 2014 and 2021.
Collaborative distances:
Collaborative distances:
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on orcid.org
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Bibliography
2021
A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique.
IEEE J. Solid State Circuits, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4<sup>th</sup> order CT-ΔΣ modulator with 2<sup>nd</sup> order noise-shaping and pipelined SAR-VCO based quantizer.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation.
IEEE J. Solid State Circuits, 2018
2017
A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2015
IEEE J. Solid State Circuits, 2015
A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015
2014
A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014