A 350 mV, 5 GHz class-D enhanced swing quadrature VCO in 65 nm CMOS with 198.3 dBc/Hz FoM. - Ankur Guha Roy; Siladitya Dey 002; Justin B. Goins; Kartikeya Mayaram; Terri S. Fiez (CICC, 2014)

A 54mW 1.2GS/s 71.5dB SNDR 50MHz BW VCO-based CT ΔΣ ADC using dual phase/frequency feedback in 65nm CMOS. - Karthikeyan Reddy; Siladitya Dey 002; Sachin Rao; Brian Young; Praveen Prabha; Pavan Kumar Hanumolu (VLSIC, 2015)

350 mV, 5 GHz Class-D Enhanced Swing Differential and Quadrature VCOs in 65 nm CMOS. - Ankur Guha Roy; Siladitya Dey 002; Justin B. Goins; Terri S. Fiez; Kartikeya Mayaram (IEEE J. Solid State Circuits, 2015)

A 50 MHz BW 73.5 dB SNDR two-stage continuous-time ΔΣ modulator with VCO quantizer nonlinearity cancellation. - Siladitya Dey 002; Karthikeyan Reddy; Kartikeya Mayaram; Terri S. Fiez (CICC, 2017)

A 50 MHz BW 76.1 dB DR Two-Stage Continuous-Time Delta-Sigma Modulator With VCO Quantizer Nonlinearity Cancellation. - Siladitya Dey 002; Karthikeyan Reddy; Kartikeya Mayaram; Terri S. Fiez (IEEE J. Solid State Circuits, 2018)

A 0.49-13.3 MHz Tunable Fourth-Order LPF with Complex Poles Achieving 28.7 dBm OIP3. - Pedram Payandehnia; Hamidreza Maghami; Hossein Mirzaie; Manjunath Kareppagoudr; Siladitya Dey 002; Massoud Tohidian; Gabor C. Temes (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

A 12 MHz BW, 80 dB SNDR, 83 dB DR, 4th order CT-ΔΣ modulator with 2nd order noise-shaping and pipelined SAR-VCO based quantizer. - Siladitya Dey 002; Kartikeya Mayaram; Terri S. Fiez (CICC, 2019)

0.9V, 79.7dB SNDR, 2MHz-BW, Highly linear OTA-less 1-1 MASH VCO-based ΔΣ with a Novel Phase Quantization Noise Extraction Technique. - Hamidreza Maghami; Pedram Payandehnia; Hossein Mirzaie; Ramin Zanbaghi; Siladitya Dey 002; Justin B. Goins; Kartikeya Mayaram; Terri S. Fiez (CICC, 2019)

A Highly Linear OTA-Free VCO-Based 1-1 MASH $ Delta Sigma$ ADC. - Hamidreza Maghami; Pedram Payandehnia; Hossein Mirzaie; Ramin Zanbaghi; Siladitya Dey 002; Kartikeya Mayaram; Terri S. Fiez (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

A Highly Linear OTA-Less 1-1 MASH VCO-Based ΔΣ ADC With an Efficient Phase Quantization Noise Extraction Technique. - Hamidreza Maghami; Pedram Payandehnia; Hossein Mirzaie; Ramin Zanbaghi; Hossein Zareie; Justin B. Goins; Siladitya Dey 002; Kartikeya Mayaram; Terri S. Fiez (IEEE J. Solid State Circuits, 2020)

A Hybrid Continuous Time Incremental and SAR Two-Step ADC with 90.5dB DR over 1MHz BW. - Yanchao Wang 001; Siladitya Dey 002; Tao He 001; Lukang Shi; Jiawei Zheng; Manjunath Kareppagoudr; Yi Zhang 023; Kazuki Sobue; Koichi Hamashita; Koji Tomioka; Gabor C. Temes (A-SSCC, 2021)