HD-BIST: a hierarchical framework for BIST scheduling and diagnosis in SOCs. - Alfredo Benso; Silvia Cataldo; Silvia Chiusano; Paolo Prinetto; Yervant Zorian (ITC, 1999)

Optimal Hardware Pattern Generation for Functional BIST. - Silvia Cataldo; Silvia Chiusano; Paolo Prinetto; Hans-Joachim Wunderlich (DATE, 2000)

A High-Level EDA Environment for the Automatic Insertion of HD-BIST Structures. - Alfredo Benso; Silvia Cataldo; Silvia Chiusano; Paolo Prinetto; Yervant Zorian (J. Electron. Test., 2000)