FIT - A Parallel Hierarchical Fault Simulation Environment. - Silvio Misera; Heinrich Theodor Vierhaus (PARELEC, 2004)

A Mixed Language Fault Simulation of VHDL and SystemC. - Silvio Misera; Heinrich Theodor Vierhaus; Lars Breitenfeld; André Sieber (DSD, 2006)

Fault Injection Techniques and their Accelerated Simulation in SystemC. - Silvio Misera; Heinrich Theodor Vierhaus; André Sieber (DSD, 2007)

Timing- / Power-Optimization for Digital Logic Based on Standard Cells. - Heinrich Theodor Vierhaus; Helmut Rossmann; Silvio Misera (DSD, 2007)

Hardwarenahe Fehlersimulation mit effektiven SystemC-Modellen. - Silvio Misera; André Sieber (MBMV, 2007)

Simulated fault injections and their acceleration in SystemC. - Silvio Misera; Heinrich Theodor Vierhaus; André Sieber (Microprocess. Microsystems, 2008)