A Reconfigurable Multiplier Array For Video Image Processing Tasks, Suitable For Embedding In An FPGA Structure. - Simon D. Haynes; Peter Y. K. Cheung (FCCM, 1998)

Algorithms and Structures for Reconfigurable Multiplication Units. - Simon D. Haynes; Antonio B. Ferrari; Peter Y. K. Cheung (SBCCI, 1998)

Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs. - Simon D. Haynes; Antonio B. Ferrari; Peter Y. K. Cheung (CICC, 1999)

SONIC - A Plug-In Architecture for Video Processing. - Simon D. Haynes; Peter Y. K. Cheung; Wayne Luk; John Stone (FCCM, 1999)

Video Image Processing with the Sonic Architecture. - Simon D. Haynes; John Stone; Peter Y. K. Cheung; Wayne Luk (Computer, 2000)

UltraSONIC: A Reconfigurable Architecture for Video Image Processing. - Simon D. Haynes; Henry G. Epsom; Richard J. Cooper; Paul L. McAlpine (FPL, 2002)

Rijndael Cryptographic Engine on the UltraSONIC Reconfigurable Platform. - Emmanuel A. Moreira; Paul L. McAlpine; Simon D. Haynes (FPL, 2002)