A 9-kbit associative memory for high-speed parallel processing applications. - Simon R. Jones; Ian P. Jalowiecki; Stephen J. Hedge; R. Mike Lea (IEEE J. Solid State Circuits, 1988)

Design and implementation of video-rate real-time systems incorporating neural networks: experiments and experience. - Simon Jones 001 (ANNES, 1993)

A Model Based Approach to the Performance Analysis of Multi-Layer Networks Realised in Linear Systolic Arrays. - David C. J. Naylor; Simon Jones 001 (IWANN, 1993)

Neural Network Feature Detector For Real-Time Video Signal Processing. - David C. J. Naylor; Simon Jones 001; David Myers; John Vincent (Int. J. Neural Syst., 1993)

Digital BiCMOS Integrated Circuit Design: Sherif H K Embabi, A. Bellaouar and Mohamed I Elmasry Kluwer Academic, Dordrecht, The Netherlands (1992) ISBN 0 7923 9276 0, £62.50, pp 432. - Simon Jones 001 (Microprocess. Microsystems, 1994)

Learning in linear systolic neural network engines: analysis and implementation. - Simon R. Jones; Karl M. Sammut; Jamie Hunter (IEEE Trans. Neural Networks, 1994)

A Performance Model for Multilayer Neural Networks in Linear Arrays. - David C. J. Naylor; Simon Jones 001 (IEEE Trans. Parallel Distributed Syst., 1994)

Asynchronous circuits based on multiple localised current-sensing completion detection. - Eckhard Grass; Simon Jones 001 (ASYNC, 1995)

Memory Management in Flash-Memory Disks with Data Compression - Morten Kjelsø; Simon Jones 001 (IWMM, 1995)

Backpropagation in linear arrays-a performance analysis and optimization. - David C. J. Naylor; Simon Jones 001; David Myers (IEEE Trans. Neural Networks, 1995)

Design and Performance of a Main Memory Hardware Data Compressor. - Morten Kjelsø; Mark Gooch; Simon Jones 001 (EUROMICRO, 1996)

VHDL-based design of biologically inspired pitch detection system. - Seow Chuan Lim; Arthur Robert Temple; Simon Jones 001; Ray Meddis (ICNN, 1997)

Biologically Inspired Pitch Detection System. - Seow Chuan Lim; Arthur Robert Temple; Simon R. Jones; Ray Meddis (ICONIP (1), 1997)

An on-line testable UART implemented using IFIS. - J. Yeandel; D. Thulborn; Simon Jones 001 (VTS, 1997)

The Design and Implementation of an On-Line Testable UART. - J. Yeandel; D. Thulborn; Simon Jones 001 (J. Electron. Test., 1998)

The X-MatchLITE FPGA-Based Data Compressor. - José Luis Núñez; Claudia Feregrino; Simon R. Jones; Stephen Bateman (EUROMICRO, 1999)

Performance evaluation of computer architectures with main memory data compression. - Morten Kjelsø; Mark Gooch; Simon Jones 001 (J. Syst. Archit., 1999)

Toward a digital neuromorphic pitch extraction system. - Simon R. Jones; Ray Meddis; Seow Chuan Lim; Arthur Robert Temple (IEEE Trans. Neural Networks Learn. Syst., 2000)

X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor. - José Luis Núñez; Claudia Feregrino; Simon R. Jones; Stephen Bateman (FPL, 2001)

FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding. - Riad Stefo; José Luis Núñez; Claudia Feregrino; Sudipta Mahapatra; Simon R. Jones (FPL, 2001)

Lossless data compression programmable hardware for high-speed data networks. - José Luis Núñez; Simon Jones 001 (FPT, 2002)

System on programmable chip for real-time control implementations. - Dario L. Sancho-Pradel; Simon R. Jones; Roger Goodall (FPT, 2002)

X-Matchpro: a High Performance Full-duplex lossless Data Compressor on a ProASIC FPGA. - José Luis Núñez; Simon Jones 001; Stephen Bateman (Int. J. Comput., 2002)

Gbit/s lossless data compression hardware. - José Luis Núñez; Simon Jones 001 (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Code Compression for the Embedded arm/Thumb Processor. - Xianhong Xu; Simon Jones 001 (Int. J. Comput., 2004)

A high-performance processor for embedded real-time control. - René Cumplido; Simon R. Jones; Roger Goodall; Stephen Bateman (IEEE Trans. Control. Syst. Technol., 2005)