A 1.6 GS/s, 16 times interleaved track & hold with 7.6 ENOB in 0.12 μm CMOS [ADC applications]. - Simon M. Louwsma; Ed J. M. van Tuijl; Maarten Vertregt; Peter C. S. Scholtens; Bram Nauta (ESSCIRC, 2004)

A CMOS switched transconductor mixer. - Eric A. M. Klumperink; Simon M. Louwsma; Gerard J. M. Wienk; Bram Nauta (IEEE J. Solid State Circuits, 2004)

A Time-Interleaved Track & hold in 0.13 μm CMOS sub-sampling a 4 GHz signal with 43 dB SNDR. - Simon M. Louwsma; Ed van Tuijl; Maarten Vertregt; Bram Nauta (CICC, 2007)

A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 µm CMOS. - Simon M. Louwsma; A. J. M. van Tuijl; Maarten Vertregt; Bram Nauta (IEEE J. Solid State Circuits, 2008)

Range pre-selection sampling technique to reduce input drive energy for SAR ADCs. - Harijot Singh Bindra; Joeri Lechevallier; Anne-Johan Annema; Simon M. Louwsma; Ed van Tuijl; Bram Nauta (A-SSCC, 2017)

An energy reduced sampling technique applied to a 10b 1MS/s SAR ADC. - Harijot Singh Bindra; Anne-Johan Annema; Simon M. Louwsma; Ed J. M. van Tuijl; Bram Nauta (ESSCIRC, 2017)

A 4MS/s 10b SAR ADC with integrated Class-A buffers in 65nm CMOS with near rail-to-rail input using a single 1.2V supply. - Harijot Singh Bindra; Anne-Johan Annema; Gerard Wienk; Bram Nauta; Simon M. Louwsma (CICC, 2019)

A 0.2 - 8 MS/s 10b flexible SAR ADC achieving 0.35 - 2.5 fJ/conv-step and using self-quenched dynamic bias comparator. - Harijot Singh Bindra; Anne-Johan Annema; Simon M. Louwsma; Bram Nauta (VLSI Circuits, 2019)

A 12.8GS/s Sub-Sampling ADC Front-End With 38GHz Input Bandwidth and >39dB SNDR for 1 to 32GHz in 22nm FDSOI. - Josef Heel; Harijot Singh Bindra; Simon M. Louwsma; Alessandro Dezzani; Bram Nauta (ISSCC, 2025)