Analog VLSI neural networks for impact signal processing. - Jeff Brauch; Simon M. Tam; Mark A. Holler; Arthur L. Shmurun (IEEE Micro, 1992)

Itanium processor clock design. - Utpal Desai; Simon M. Tam; Robert Kim; Ji Zhang; Stefan Rusu (ISPD, 2000)

Clock generation and distribution for the first IA-64 microprocessor. - Simon Tam 001; Stefan Rusu; Utpal Nagarji Desai; Robert Kim; Ji Zhang; Ian Young 001 (IEEE J. Solid State Circuits, 2000)

A 1.5-GHz 130-nm Itanium® 2 Processor with 6-MB on-die L3 cache. - Stefan Rusu; Jason Stinson; Simon Tam 001; Justin Leung; Harry Muljono; Brian S. Cherkauer (IEEE J. Solid State Circuits, 2003)

Clock generation and distribution for the 130-nm Itanium® 2 processor with 6-MB on-die L3 cache. - Simon Tam 001; Rahul Dilip Limaye; Utpal Nagarji Desai (IEEE J. Solid State Circuits, 2004)

A 130-nm triple-Vt 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor. - Jonathan Chang; Stefan Rusu; Jonathan Shoemaker; Simon Tam 001; Ming Huang; Mizan Haque; Siufu Chiu; Kevin Truong; Mesbah Karim; Gloria Leong; Kiran Desai; Richard Goe; et al. (IEEE J. Solid State Circuits, 2005)

A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache. - Stefan Rusu; Simon M. Tam; Harry Muljono; David Ayers; Jonathan Chang (ISSCC, 2006)

Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache. - Simon Tam 001; Justin Leung; Rahul Dilip Limaye; Sam Choy; Sujal Vora; Mitsuhiro Adachi (ISSCC, 2006)

Novel compensation scheme for local clocks of high performance microprocessors. - Cecilia Metra; Martin Omaña 001; T. M. Mak; Simon Tam 001 (ITC, 2007)

Novel Approach to Clock Fault Testing for High Performance Microprocessors. - Cecilia Metra; Martin Omaña 001; T. M. Mak; Simon Tam 001 (VTS, 2007)

A 65-nm Dual-Core Multithreaded Xeon® Processor With 16-MB L3 Cache. - Stefan Rusu; Simon M. Tam; Harry Muljono; David Ayers; Jonathan Chang; Brian S. Cherkauer; Jason Stinson; John Benoit; Raj Varada; Justin Leung; Rahul Dilip Limaye; Sujal Vora (IEEE J. Solid State Circuits, 2007)

Novel On-Chip Clock Jitter Measurement Scheme for High Performance Microprocessors. - Cecilia Metra; Martin Omaña 001; T. M. Mak; Asifur Rahman; Simon Tam 001 (DFT, 2008)

Power reduction techniques for an 8-core xeon® processor. - Stefan Rusu; Simon M. Tam; Harry Muljono; Jason Stinson; David Ayers; Jonathan Chang; Raj Varada; Matt Ratta; Sailesh Kottapalli; Sujal Vora (ESSCIRC, 2009)

A 45nm 8-core enterprise Xeon® processor. - Stefan Rusu; Simon M. Tam; Harry Muljono; Jason Stinson; David Ayers; Jonathan Chang; Raj Varada; Matt Ratta; Sailesh Kottapalli (ISSCC, 2009)

On-die Ring Oscillator Based Measurement Scheme for Process Parameter Variations and Clock Jitter. - Martin Omaña 001; Daniele Giaffreda; Cecilia Metra; T. M. Mak; Simon Tam 001; Asifur Rahman (DFT, 2010)

A 45 nm 8-Core Enterprise Xeon¯ Processor. - Stefan Rusu; Simon M. Tam; Harry Muljono; Jason Stinson; David Ayers; Jonathan Chang; Raj Varada; Matt Ratta; Sailesh Kottapalli; Sujal Vora (IEEE J. Solid State Circuits, 2010)

Low-Cost Dynamic Compensation Scheme for Local Clocks of Next Generation High Performance Microprocessors. - Martin Omaña 001; Cecilia Metra; T. M. Mak; Simon Tam 001 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

New Design for Testability Approach for Clock Fault Testing. - Cecilia Metra; Martin Omaña 001; T. M. Mak; Simon Tam 001 (IEEE Trans. Computers, 2012)

Active Filter-Based Hybrid On-Chip DC-DC Converter for Point-of-Load Voltage Regulation. - Selçuk Köse; Simon Tam 001; Sally Pinzon; Bruce McDermott; Eby G. Friedman (IEEE Trans. Very Large Scale Integr. Syst., 2013)

5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family. - Stefan Rusu; Harry Muljono; David Ayers; Simon M. Tam; Wei Chen 129; Aaron Martin; Shenggao Li; Sujal Vora; Raj Varada; Eddie Wang (ISSCC, 2014)

A 22 nm 15-Core Enterprise Xeon® Processor Family. - Stefan Rusu; Harry Muljono; David Ayers; Simon M. Tam; Wei Chen 129; Aaron Martin; Shenggao Li; Sujal Vora; Raj Varada; Eddie Wang (IEEE J. Solid State Circuits, 2015)

Low-Cost On-Chip Clock Jitter Measurement Scheme. - Martin Omaña 001; Daniele Rossi 001; Daniele Giaffreda; Cecilia Metra; T. M. Mak; Asifur Rahman; Simon Tam 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

SkyLake-SP: A 14nm 28-Core xeon® processor. - Simon M. Tam; Harry Muljono; Min Huang; Sitaraman Iyer; Kalapi Royneogi; Nagmohan Satti; Rizwan Qureshi; Wei Chen 129; Tom Wang; Hubert Hsieh; Sujal Vora; Eddie Wang (ISSCC, 2018)