Asynchronous parallel MPSoC simulation on the Single-Chip Cloud Computer. - Christoph Roth; Simon Reder; Gokhan Erdogan; Oliver Sander; Gabriel Marchesan Almeida; Harald Bucher; Jürgen Becker 001 (ISSoC, 2012)

A Framework for exploration of parallel SystemC simulation on the single-chip cloud computer. - Christoph Roth; Simon Reder; Oliver Sander; Michael Hübner 001; Jürgen Becker 001 (SimuTools, 2012)

Improving parallel MPSoC simulation performance by exploiting dynamic routing delay prediction. - Christoph Roth; Harald Bucher; Simon Reder; Oliver Sander; Jürgen Becker 001 (ReCoSoC, 2013)

A SystemC modeling and simulation methodology for fast and accurate parallel MPSoC simulation. - Christoph Roth; Harald Bucher; Simon Reder; Florian Buciuman; Oliver Sander; Jürgen Becker 001 (SBCCI, 2013)

Adaptive Algorithm and Tool Flow for Accelerating System C on Many-Core Architectures. - Christoph Roth; Simon Reder; Harald Bucher; Oliver Sander; Jürgen Becker 001 (DSD, 2014)

Adaptive algorithm and tool flow for accelerating SystemC on many-core architectures. - Simon Reder; Christoph Roth; Harald Bucher; Oliver Sander; Jürgen Becker 001 (Microprocess. Microsystems, 2015)

WCET-aware parallelization of model-based applications for multi-cores: The ARGO approach. - Steven Derrien; Isabelle Puaut; Panayiotis Alefragis; Marcus Bednara; Harald Bucher; Clément David; Yann Debray; Umut Durak; Imen Fassi; Christian Ferdinand; Damien Hardy; Angeliki Kritikakou; et al. (DATE, 2017)

Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach. - Panayiotis Alefragis; George Theodoridis; Merkourios Katsimpris; Christos Valouxis; Christos Gogos; George Goulas; Nikolaos S. Voros; Simon Reder; Koray Kasnakli; Marcus Bednara; David Müller 005; Umut Durak; et al. (ARC, 2018)

A WCET-aware parallel programming model for predictability enhanced multi-core architectures. - Simon Reder; Leonard Masing; Harald Bucher; Timon D. ter Braak; Timo Stripf; Jürgen Becker 001 (DATE, 2018)

Worst-Case Execution-Time-Aware Parallelization of Model-Based Avionics Applications. - Simon Reder; Fabian Kempf; Harald Bucher; Jürgen Becker 001; Panayiotis Alefragis; Nikolaos S. Voros; Stefanos Skalistis; Steven Derrien; Isabelle Puaut; Oliver Oey; Timo Stripf; Christian Ferdinand; et al. (J. Aerosp. Inf. Syst., 2019)

WCET-aware Code Generation and Communication Optimization for Parallelizing Compilers. - Simon Reder; Jürgen Becker 001 (DATE, 2020)

Interference-Aware Memory Allocation for Real-Time Multi-Core Systems. - Simon Reder; Jürgen Becker 001 (RTAS, 2020)

Compileroptimierung und parallele Code-Generierung für zeitkritische eingebettete Multiprozessorsysteme. - Simon Reder (2020)