Exploration of Fault Effects on Formal RISC-V Microarchitecture Models. - Simon Tollec; Mihail Asavoae; Damien Couroussé; Karine Heydemann; Mathieu Jan (FDTC, 2022)

μARCHIFI: Formal Modeling and Verification Strategies for Microarchitectural Fault Injections. - Simon Tollec; Mihail Asavoae; Damien Couroussé; Karine Heydemann; Mathieu Jan (FMCAD, 2023)

Fault-Resistant Partitioning of Secure CPUs for System Co-Verification against Faults. - Simon Tollec; Vedad Hadzic; Pascal Nasahl; Mihail Asavoae; Roderick Bloem; Damien Couroussé; Karine Heydemann; Mathieu Jan; Stefan Mangard (IACR Cryptol. ePrint Arch., 2024)

Formal verification of processor microarchitecture to analyze system security against fault attacks. (Vérification formelle de la micro-architecture de processeurs pour l'analyse de sécurité des systèmes contre les attaques par injection de fautes). - Simon Tollec (2024)