A 10Gb/s receiver with linear backplane equalization and mixer-based self-aligned CDR. - Simone Erba; Massimo Pozzoni; Matteo Pisati; Riccardo Brama; Davide Sanzogni; Emanuele Depaoli; Paolo Viola; Francesco Svelto (CICC, 2008)

A Multi-Standard 1.5 to 10 Gb/s Latch-Based 3-Tap DFE Receiver With a SSC Tolerant CDR for Serial Backplane Communication. - Massimo Pozzoni; Simone Erba; Paolo Viola; Matteo Pisati; Emanuele Depaoli; Davide Sanzogni; Riccardo Brama; Daniele Baldi; Matteo Repossi; Francesco Svelto (IEEE J. Solid State Circuits, 2009)

A 12Gb/s 39dB loss-recovery unclocked-DFE receiver with bi-dimensional equalization. - Massimo Pozzoni; Simone Erba; Davide Sanzogni; Marcello Ganzerli; Paolo Viola; Daniele Baldi; Matteo Repossi; Giorgio Spelgatti; Francesco Svelto (ISSCC, 2010)

An inductor-less 13.5-Gbps 8-mW analog equalizer for multi-channel multi-frequency operation. - Marcello Ganzerli; Luca Larcher; Simone Erba; Davide Sanzogni (ISCAS, 2011)

A 0.2-11.7GHz, high accuracy injection-locking multi-phase generation with mixed analog/digital calibration loops in 28nm FDSOI CMOS. - Gabriele Anzalone; Enrico Monaco; Guido Albasini; Simone Erba; Andrea Mazzanti (ESSCIRC, 2016)

3.6 A 45Gb/s PAM-4 transmitter delivering 1.3Vppd output swing with 1V supply in 28nm CMOS FDSOI. - Matteo Bassi; Francesco Radice; Melchiorre Bruccoleri; Simone Erba; Andrea Mazzanti (ISSCC, 2016)

Session 23 overview: Electrical and optical link innovations. - Frank O'Mahony; Simone Erba (ISSCC, 2016)

A High-Swing 45 Gb/s Hybrid Voltage and Current-Mode PAM-4 Transmitter in 28 nm CMOS FDSOI. - Matteo Bassi; Francesco Radice; Melchiorre Bruccoleri; Simone Erba; Andrea Mazzanti (IEEE J. Solid State Circuits, 2016)

Session 6 overview: Ultra-high-speed wireline. - Simone Erba; Takayuki Shibasaki; Frank O'Mahony (ISSCC, 2017)

F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyond. - Yohan Frans; Ichiro Fujimori; Seung-Jun Bae; Samuel Palermo; Hideyuki Nosaka; Simone Erba (ISSCC, 2017)

6.4 A 64Gb/s PAM-4 transmitter with 4-Tap FFE and 2.26pJ/b energy efficiency in 28nm CMOS FDSOI. - Giovanni Steffan; Emanuele Depaoli; Enrico Monaco; Nicolo Sabatino; Walter Audoglio; Augusto Andrea Rossi; Simone Erba; Matteo Bassi; Andrea Mazzanti (ISSCC, 2017)

A 2-11 GHz 7-Bit High-Linearity Phase Rotator Based on Wideband Injection-Locking Multi-Phase Generation for High-Speed Serial Links in 28-nm CMOS FDSOI. - Enrico Monaco; Gabriele Anzalone; Guido Albasini; Simone Erba; Matteo Bassi; Andrea Mazzanti (IEEE J. Solid State Circuits, 2017)

A 25mW Highly Linear Continuous-Time FIR Equalizer for 25Gb/s Serial Links in 28-nm CMOS. - Fabrizio Loi; Enrico Mammei; Simone Erba; Matteo Bassi; Andrea Mazzanti (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

A 4.9pJ/b 16-to-64Gb/s PAM-4 VSR transceiver in 28nm FDSOI CMOS. - Emanuele Depaoli; Enrico Monaco; Giovanni Steffan; Marco Mazzini; Hongyang Zhang; Walter Audoglio; Oscar Belotti; Augusto Andrea Rossi; Guido Albasini; Massimo Pozzoni; Simone Erba; Andrea Mazzanti (ISSCC, 2018)

F5: Advanced optical communication: From devices, circuits, and architectures to algorithms. - Bo Zhang; Frederic Gianesello; Simone Erba; Mounir Meghelli; Azita Emami; Takayuki Shibasaki (ISSCC, 2018)

A 64 Gb/s Low-Power Transceiver for Short-Reach PAM-4 Electrical Links in 28-nm FDSOI CMOS. - Emanuele Depaoli; Hongyang Zhang; Marco Mazzini; Walter Audoglio; Augusto Andrea Rossi; Guido Albasini; Massimo Pozzoni; Simone Erba; Enrico Temporiti; Andrea Mazzanti (IEEE J. Solid State Circuits, 2019)

A K-band Gilbert-Cell Frequency Doubler with Self-Adjusted 25% LO Duty-Cycle in SiGe BiCMOS Technology. - Lorenzo Piotto; Guglielmo De Filippi; Daniele Dal Maistro; Simone Erba; Andrea Mazzanti (ESSCIRC, 2022)

A 14-32 GHz SiGe-BiCMOS Gilbert-Cell Frequency Doubler With Self-Adjusted Reduced Duty-Cycle Performance Enhancement. - Lorenzo Piotto; Guglielmo De Filippi; Gianluca Brozzetti; Daniele Dal Maistro; Simone Erba; Andrea Mazzanti (IEEE J. Solid State Circuits, 2024)