A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter. - Mario Mercandelli; Alessio Santiccioli; Simone Mattia Dartizio; Abanob Shehata; Francesco Tesolin; Saleh Karman; Luca Bertulessi; Francesco Buccoleri; Luca Avallone; Angelo Parisi; Andrea Leonardo Lacaita; Michael Peter Kennedy; et al. (ISSCC, 2021)

32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays. - Alessio Santiccioli; Mario Mercandelli; Simone Mattia Dartizio; Francesco Tesolin; Saleh Karman; Abanob Shehata; Luca Bertulessi; Francesco Buccoleri; Luca Avallone; Angelo Parisi; Dmytro Cherniak; Andrea L. Lacaita; et al. (ISSCC, 2021)

A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler. - Francesco Buccoleri; Simone Mattia Dartizio; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Andrea Bevilacqua; Luca Bertulessi; Dmytro Cherniak; Carlo Samori; Andrea L. Lacaita; et al. (CICC, 2022)

A 68.6fsrms-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching. - Simone Mattia Dartizio; Francesco Buccoleri; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea Leonardo Lacaita; et al. (ISSCC, 2022)

A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time. - Simone Mattia Dartizio; Francesco Buccoleri; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea L. Lacaita; et al. (IEEE J. Solid State Circuits, 2022)

A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping. - Simone Mattia Dartizio; Francesco Tesolin; Mario Mercandelli; Alessio Santiccioli; Abanob Shehata; Saleh Karman; Luca Bertulessi; Francesco Buccoleri; Luca Avallone; Angelo Parisi; Andrea L. Lacaita; Michael Peter Kennedy; et al. (IEEE J. Solid State Circuits, 2022)

A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology. - Giacomo Castoro; Simone Mattia Dartizio; Francesco Tesolin; Francesco Buccoleri; Michele Rossoni; Dmytro Cherniak; Luca Bertulessi; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (ISSCC, 2023)

A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. - Simone Mattia Dartizio; Francesco Tesolin; Giacomo Castoro; Francesco Buccoleri; Luca Lanzoni; Michele Rossoni; Dmytro Cherniak; Luca Bertulessi; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (ISSCC, 2023)

Design of small-footprint, high-spectral purity and low-jitter digitally-intensive frequency synthetizers - Simone Mattia Dartizio (2023)

Phase Noise Analysis of Periodically ON/OFF Switched Oscillators. - Giacomo Castoro; Simone Mattia Dartizio; Andrea L. Lacaita; Salvatore Levantino (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner. - Francesco Buccoleri; Simone Mattia Dartizio; Francesco Tesolin; Luca Avallone; Alessio Santiccioli; Agata Iesurum; Giovanni Steffan; Dmytro Cherniak; Luca Bertulessi; Andrea Bevilacqua; Carlo Samori; Andrea L. Lacaita; et al. (IEEE J. Solid State Circuits, 2023)

A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays. - Francesco Tesolin; Simone Mattia Dartizio; Francesco Buccoleri; Alessio Santiccioli; Luca Bertulessi; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2023)

A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering. - Simone Mattia Dartizio; Francesco Tesolin; Giacomo Castoro; Francesco Buccoleri; Michele Rossoni; Dmytro Cherniak; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2023)

A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector. - Simone Mattia Dartizio; Michele Rossoni; Francesco Tesolin; Giacomo Castoro; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (CICC, 2024)

A 66.7fs-Integrated-Jitter Fractional-N Digital PLL Based on a Resistive-Inverse-Constant-Slope DTC. - Pietro Salvi; Simone Mattia Dartizio; Michele Rossoni; Francesco Tesolin; Giacomo Castoro; Andrea L. Lacaita; Salvatore Levantino (CICC, 2024)

10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM. - Michele Rossoni; Simone Mattia Dartizio; Francesco Tesolin; Giacomo Castoro; Riccardo Dell'Orto; Carlo Samori; Andrea Leonardo Lacaita; Salvatore Levantino (ISSCC, 2024)

10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion. - Francesco Tesolin; Simone Mattia Dartizio; Giacomo Castoro; Francesco Buccoleri; Michele Rossoni; Dmytro Cherniak; Carlo Samori; Andrea Leonardo Lacaita; Salvatore Levantino (ISSCC, 2024)

A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique. - Riccardo Moleri; Simone Mattia Dartizio; Michele Rossoni; Giacomo Castoro; Francesco Tesolin; Dmytro Cherniak; Carlo Samori; Andrea Leonardo Lacaita; Salvatore Levantino (VLSI Technology and Circuits, 2024)

A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars. - Francesco Tesolin; Simone Mattia Dartizio; Giacomo Castoro; Francesco Buccoleri; Michele Rossoni; Carlo Samori; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2024)

34.2 A 380μW and -242.8dB FoM Digital-PLL-Based GFSK Modulator with Sub-20μs Settling Frequency Hopping for Bluetooth Low-Energy in 22nm CMOS. - Simone Mattia Dartizio; Giacomo Castoro; Stefano Gallucci; Michele Rossoni; Riccardo Moleri; Francesco Tesolin; Pietro Salvi; Saleh Karman; Andrea Leonardo Lacaita; Salvatore Levantino (ISSCC, 2025)

34.3 A 4.75GHz Digital PLL with 45.8fs Integrated-Jitter and 257dB FoM Based on a Voltage-Biased Harmonic-Shaping DCO with Adaptive Common-Mode Resonance Tuning. - Stefano Gallucci; Francesco Tesolin; Pietro Salvi; Daniele Lodi Rizzini; Riccardo Moleri; Francesco Buccoleri; Michele Rossoni; Giacomo Castoro; Simone Mattia Dartizio; Carlo Samori; Andrea Leonardo Lacaita; Salvatore Levantino (ISSCC, 2025)

A Low-Jitter Fractional- N Digital PLL Adopting a Reverse-Concavity Variable-Slope DTC. - Michele Rossoni; Simone Mattia Dartizio; Francesco Tesolin; Giacomo Castoro; Riccardo Dell'Orto; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2025)

A Low-Noise Fractional-N Digital PLL Using a Resistor-Based Inverse-Constant-Slope DTC. - Pietro Salvi; Simone Mattia Dartizio; Michele Rossoni; Francesco Tesolin; Giacomo Castoro; Andrea L. Lacaita; Salvatore Levantino (IEEE J. Solid State Circuits, 2025)