Interior spikes of a singularly perturbed Neumann problem with potentials. - A. Pomponio; Simone Secchi (Appl. Math. Lett., 2004)

A Surface Tension and Coalescence Model for Dynamic Distributed Resources Allocation in Massively Parallel Processors on-Chip. - Francesca Palumbo; Danilo Pani; Luigi Raffo; Simone Secchi (NICSO, 2007)

A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching. - Simone Secchi; Francesca Palumbo; Danilo Pani; Luigi Raffo (DSD, 2008)

A Novel Non-exclusive Dual-Mode Architecture for MPSoCs-Oriented Network on Chip Designs. - Francesca Palumbo; Simone Secchi; Danilo Pani; Luigi Raffo (SAMOS, 2008)

Self organization on a swarm computing fabric: a new way to look at fault tolerance. - Danilo Pani; Simone Secchi; Luigi Raffo (Conf. Computing Frontiers, 2010)

Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures. - Simone Secchi; Paolo Meloni; Luigi Raffo (ISPASS, 2010)

Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper. - Paolo Meloni; Simone Secchi; Luigi Raffo (VLSI-SoC, 2010)

An FPGA-Based Framework for Technology-Aware Prototyping of Multicore Embedded Architectures. - Paolo Meloni; Simone Secchi; Luigi Raffo (IEEE Embed. Syst. Lett., 2010)

Experiences with String Matching on the Fermi Architecture. - Antonino Tumeo; Simone Secchi; Oreste Villa (ARCS, 2011)

Contention Modeling for Multithreaded Distributed Shared Memory Machines: The Cray XMT. - Simone Secchi; Antonino Tumeo; Oreste Villa (CCGRID, 2011)

Irregular applications: architectures & algorithms. - John Feo; Oreste Villa; Antonino Tumeo; Simone Secchi (IA3@SC, 2011)

Towards efficient execution of irregular applications: panel outline. - John Feo; Oreste Villa; Antonino Tumeo; Simone Secchi (IA3@SC, 2011)

A Bandwidth-Optimized Multi-core Architecture for Irregular Applications. - Simone Secchi; Antonino Tumeo; Oreste Villa (CCGRID, 2012)

Efficient Sorting on the Tilera Manycore Architecture. - Alessandro Morari; Antonino Tumeo; Oreste Villa; Simone Secchi; Mateo Valero (SBAC-PAD, 2012)

Designing Next-Generation Massively Multithreaded Architectures for Irregular Applications. - Antonino Tumeo; Simone Secchi; Oreste Villa (Computer, 2012)

Fast and Accurate Simulation of the Cray XMT Multithreaded Supercomputer. - Oreste Villa; Antonino Tumeo; Simone Secchi; Joseph B. Manzano (IEEE Trans. Parallel Distributed Syst., 2012)

Enabling Fast ASIP Design Space Exploration: An FPGA-Based Runtime Reconfigurable Prototyper. - Paolo Meloni; Sebastiano Pomata; Giuseppe Tuveri; Simone Secchi; Luigi Raffo; Menno Lindwer (VLSI Design, 2012)

Exploring hardware support for scaling irregular applications on multi-node multi-core architectures. - Simone Secchi; Marco Ceriani; Antonino Tumeo; Oreste Villa; Gianluca Palermo; Luigi Raffo (ASAP, 2013)

A runtime adaptive H.264 video-decoding MPSoC platform. - Giuseppe Tuveri; Simone Secchi; Paolo Meloni; Luigi Raffo; Emanuele Cannella (DASIP, 2013)

Exploring manycore multinode systems for irregular applications with FPGA prototyping. - Marco Ceriani; Simone Secchi; Antonino Tumeo; Oreste Villa; Gianluca Palermo (Hot Chips Symposium, 2013)

Prototyping hardware support for irregular applications. - Marco Ceriani; Simone Secchi; Antonino Tumeo; Oreste Villa (RAPIDO, 2013)

Special Issue on Architectures and Algorithms for Irregular Applications (AAIA) - Guest editors' introduction. - Antonino Tumeo; John Feo; Oreste Villa; Simone Secchi; Timothy G. Mattson (J. Parallel Distributed Comput., 2015)

Exploring Efficient Hardware Support for Applications with Irregular Memory Patterns on Multinode Manycore Architectures. - Marco Ceriani; Simone Secchi; Oreste Villa; Antonino Tumeo; Gianluca Palermo (IEEE Trans. Parallel Distributed Syst., 2017)

A Note on Sign-Changing Solutions to the NLS on the Double-Bridge Graph. - Diego Noja; Sergio Rolando; Simone Secchi (Symmetry, 2019)