Diagnosis of Transistor Shorts in Logic Test Environment. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Sin-ya Kobayashi; Yuzo Takamatsu (ATS, 2006)

An Algorithm for Diagnosing Transistor Shorts Using Gate-level Simulation. - Yoshinobu Higami; Kewal K. Saluja; Hiroshi Takahashi; Sin-ya Kobayashi; Yuzo Takamatsu (Inf. Media Technol., 2009)