A Variable-Way Address Translation Cache for the Exascale Supercomputer. - Tiejun Li; Jianmin Zhang; Siqing Fu; Kefan Ma (ICA3PP (3), 2021)

MiniMCTAD: Minimalist Monte Carlo Transport Architecture Design. - Siqing Fu; Tiejun Li; Jianmin Zhang; Sheng Ma; Sheng Liu (ISPA/BDCloud/SocialCom/SustainCom, 2021)

An Incomplete Unsatisfiable Cores Extracting Algorithm to Promote Routing. - Jianmin Zhang; Tiejun Li; Siqing Fu (QRS, 2021)

RHS-TRNG: A Resilient High-Speed True Random Number Generator Based on STT-MTJ Device. - Siqing Fu; Tiejun Li; Chunyuan Zhang; Hanqing Li; Sheng Ma; Jianmin Zhang; Ruiyi Zhang; Lizhou Wu (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Spin-NeuroMem: A Low-Power Neuromorphic Associative Memory Design Based on Spintronic Devices. - Siqing Fu; Tiejun Li; Chunyuan Zhang; Sheng Ma; Jianmin Zhang; Lizhou Wu (CoRR, 2024)

SFC-TRNG: A Stable Fast and Compact True Random Number Generator based on Magnetic Tunnel Junction. - Yu Ma; Yan Sun; Jianmin Zhang; Siqing Fu (ACM Great Lakes Symposium on VLSI, 2025)

NeuroPDE: A Neuromorphic PDE Solver Based on Spintronic and Ferroelectric Devices. - Siqing Fu; Lizhou Wu; Tiejun Li; Chunyuan Zhang; Sheng Ma; Jianmin Zhang; Yuhan Tang; Jixuan Tang (CoRR, 2025)