MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level. - Sitaran Yadavalli; Irith Pomeranz; Sudhakar M. Reddy (VLSI Design, 1995)

SymSim: symbolic fault simulation of data-flow data-path designs at the Register-Transfer level. - Sitaran Yadavalli; Sudhakar M. Reddy (ITC, 1999)