FPGA realisation of PSNR and BPP driven Adaptive Compression and Encryption Algorithm for RGB Images. - Pranose J. Edavoor; Sithara Raveendran; Arjun T. V.; Sumesh K. P.; Kumar Y. B. Nithin; M. H. Vasantha (ICCCNT, 2016)

Characterization of a Novel Low Leakage Power and Area Efficient 7T SRAM Cell. - A. Venkatareddy; Sithara Raveendran; Kumar Y. B. Nithin; M. H. Vasantha (VLSID, 2016)

Design and implementation of PID controller based on orthogonal wavelet filter-banks in FPGA. - Priyanandini Das; Pranose J. Edavoor; Sithara Raveendran; Sunil Rathore; Amol D. Rahulkar (ISED, 2017)

Implementation of adaptive image compression algorithm using varying bit-length daubechies wavelet coefficient with three-level encryption on Zynq 7000. - Pranose J. Edavoor; Sithara Raveendran; Amol D. Rahulkar (ISED, 2017)

FPGA Implementation of Square and Cube Architecture Using Vedic Mathematics. - Sampada Barve; Sithara Raveendran; Charudatta Korde; Trilochan Panigrahi; Nithin Y. B. Kumar; M. H. Vasantha (iSES, 2018)

Design and Implementation of Reversible Logic based RGB to Gray scale Color Space Converter. - Sithara Raveendran; Pranose J. Edavoor; Nithin Y. B. Kumar; M. H. Vasantha (TENCON, 2018)

Design and Analysis of Energy Efficient Reversible Logic based Full Adder. - Jagadeesh Pujar; Sithara Raveendran; Trilochan Panigrahi; Vasantha M. H.; Nithin Kumar Y. B. (MWSCAS, 2019)

Reversible Logic Implementation of Image Denoising for Grayscale Images. - Sithara Raveendran; Pranose J. Edavoor; Nithin Kumar Y. B.; M. H. Vasantha (MWSCAS, 2020)

Approximate Multiplier Design Using Novel Dual-Stage 4: 2 Compressors. - Pranose J. Edavoor; Sithara Raveendran; Amol D. Rahulkar (IEEE Access, 2020)

An Approximate Low-Power Lifting Scheme Using Reversible Logic. - Sithara Raveendran; Pranose J. Edavoor; Nithin Y. B. Kumar; M. H. Vasantha (IEEE Access, 2020)

Design and implementation of image kernels using reversible logic gates. - Sithara Raveendran; Pranose J. Edavoor; Nithin Kumar Yernad Balachandra; Vasantha Moodabettu Harishchandra (IET Image Process., 2020)

Inexact Signed Wallace Tree Multiplier Design Using Reversible Logic. - Sithara Raveendran; Pranose J. Edavoor; Nithin Kumar Yernad Balachandra; M. H. Vasantha (IEEE Access, 2021)

Novel 4: 2 Approximate Compressor Designs for Multimedia and Neural Network Applications. - Pranose J. Edavoor; Sithara Raveendran; Amol D. Rahulkar (J. Circuits Syst. Comput., 2021)

On The Design Of Rationalised Bi-orthogonal Wavelet Using Reversible Logic. - Sithara Raveendran; Pranose J. Edavoor; Y. B. Nithin Kumar; M. H. Vasantha (ISCAS, 2022)

Approximate Three-Operand Binary Adder for Error-Resilient Applications. - Darshan Halliyavar; Siddharth R. K.; Vasantha M. H.; Nithin Kumar Y. B.; Sithara Raveendran (iSES, 2023)