A 130-nm triple-Vt 9-MB third-level on-die cache for the 1.7-GHz Itanium® 2 processor. - Jonathan Chang; Stefan Rusu; Jonathan Shoemaker; Simon Tam 001; Ming Huang; Mizan Haque; Siufu Chiu; Kevin Truong; Mesbah Karim; Gloria Leong; Kiran Desai; Richard Goe; et al. (IEEE J. Solid State Circuits, 2005)

The 65-nm 16-MB Shared On-Die L3 Cache for the Dual-Core Intel Xeon Processor 7100 Series. - Jonathan Chang; Ming Huang; Jonathan Shoemaker; John Benoit; Szu-Liang Chen; Wei Chen 129; Siufu Chiu; Raghuraman Ganesan; Gloria Leong; Venkata Lukka; Stefan Rusu; Durgesh Srivastava (IEEE J. Solid State Circuits, 2007)