MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns. - James T. Kao; Siva G. Narendra; Anantha P. Chandrakasan (DAC, 1998)

Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's. - Ali Keshavarzi; Siva G. Narendra; Shekhar Borkar; Charles F. Hawkins; Kaushik Roy 001; Vivek De (ISLPED, 1999)

Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs. - Ali Keshavarzi; Sean Ma; Siva G. Narendra; Brad Bloechel; K. Mistry; Tahir Ghani; Shekhar Borkar; Vivek De (ISLPED, 2001)

Scaling of stack effect and its application for leakage reduction. - Siva G. Narendra; Vivek De; Dimitri A. Antoniadis; Anantha P. Chandrakasan; Shekhar Borkar (ISLPED, 2001)

Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. - James W. Tschanz; Siva G. Narendra; Zhanping Chen; Shekhar Borkar; Manoj Sachdev; Vivek De (ISLPED, 2001)

Subthreshold leakage modeling and reduction techniques. - James T. Kao; Siva G. Narendra; Anantha P. Chandrakasan (ICCAD, 2002)

Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. - Siva G. Narendra; Vivek De; Shekhar Borkar; Dimitri A. Antoniadis; Anantha P. Chandrakasan (ISLPED, 2002)

Evening Panel Discussion: Process Variation: Is It Too Much to Handle? - Ron Wilson; Siva G. Narendra; Vivek De (ISQED, 2002)

Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. - Ali Keshavarzi; James W. Tschanz; Siva G. Narendra; Vivek De; W. Robert Daasch; Kaushik Roy 001; Manoj Sachdev; Charles F. Hawkins (IEEE Des. Test Comput., 2002)

Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. - James W. Tschanz; James T. Kao; Siva G. Narendra; Raj Nair; Dimitri A. Antoniadis; Anantha P. Chandrakasan; Vivek De (IEEE J. Solid State Circuits, 2002)

5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS. - Sriram R. Vangal; Mark A. Anders 001; Nitin Borkar; Erik Seligman; Venkatesh Govindarajulu; Vasantha Erraguntla; Howard Wilson; Amaresh Pangal; Venkat Veeramachaneni; James W. Tschanz; Yibin Ye; Dinesh Somasekhar; et al. (IEEE J. Solid State Circuits, 2002)

Analysis of dual-VT SRAM cells with full-swing single-ended bit line sensing for on-chip cache. - Fatih Hamzaoglu; Yibin Ye; Ali Keshavarzi; Kevin Zhang 001; Siva G. Narendra; Shekhar Borkar; Mircea R. Stan; Vivek De (IEEE Trans. Very Large Scale Integr. Syst., 2002)

Effect of Metal oxide semiconductor field-effect transistors threshold voltage variation on high-performance circuits. - Siva G. Narendra (2002)

Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. - Peter Hazucha; Tanay Kamik; Steven Walstra; Bradley A. Bloechel; James W. Tschanz; Jose Maiz; Krishnamurthy Soumyanath; Greg Dermer; Siva G. Narendra; Vivek De; Shekhar Borkar (CICC, 2003)

Parameter variations and impact on circuits and microarchitecture. - Shekhar Borkar; Tanay Karnik; Siva G. Narendra; James W. Tschanz; Ali Keshavarzi; Vivek De (DAC, 2003)

Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation. - Stephen Tang; Siva G. Narendra; Vivek De (ISLPED, 2003)

Monolithic DC-DC Converter Analysis And Mosfet Gate Voltage Optimization. - Volkan Kursun; Siva G. Narendra; Vivek De; Eby G. Friedman (ISQED, 2003)

A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS. - Yatin Vasant Hoskote; Bradley A. Bloechel; Gregory E. Dermer; Vasantha Erraguntla; David Finan; Jason Howard; Dan Klowden; Siva G. Narendra; Greg Ruhl; James W. Tschanz; Sriram R. Vangal; Venkat Veeramachaneni; et al. (IEEE J. Solid State Circuits, 2003)

Forward body bias for microprocessors in 130-nm technology generation and beyond. - Siva G. Narendra; Ali Keshavarzi; Bradley A. Bloechel; Shekhar Borkar; Vivek De (IEEE J. Solid State Circuits, 2003)

Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors. - James W. Tschanz; Siva G. Narendra; Raj Nair; Vivek De (IEEE J. Solid State Circuits, 2003)

Dynamic sleep transistor and body bias for active leakage power control of microprocessors. - James W. Tschanz; Siva G. Narendra; Yibin Ye; Bradley A. Bloechel; Shekhar Borkar; Vivek De (IEEE J. Solid State Circuits, 2003)

Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor. - Volkan Kursun; Siva G. Narendra; Vivek De; Eby G. Friedman (IEEE Trans. Very Large Scale Integr. Syst., 2003)

Design optimizations for microprocessors at low temperature. - Arman Vassighi; Ali Keshavarzi; Siva G. Narendra; Gerhard Schrom; Yibin Ye; Seri Lee; Greg Chrysler; Manoj Sachdev; Vivek De (DAC, 2004)

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation. - Gerhard Schrom; Peter Hazucha; Jae-Hong Hahn; Volkan Kursun; Donald S. Gardner; Siva G. Narendra; Tanay Karnik; Vivek De (ISLPED, 2004)

High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process. - Volkan Kursun; Siva G. Narendra; Vivek De; Eby G. Friedman (ISQED, 2004)

The Influence of Process Variations on the Halo MOSFETs and its Implications on the Analog Circuit performance. - K. Narasimhulu; Siva G. Narendra; V. Ramgopal Rao (VLSI Design, 2004)

Design Challenges in Sub-100nm High Performance Microprocessors. - Siva G. Narendra; Vasantha Erraguntla; James W. Tschanz; Nitin Borkar (VLSI Design, 2004)

Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process. - Peter Hazucha; Tanay Karnik; Steven Walstra; Bradley A. Bloechel; James W. Tschanz; Jose Maiz; Krishnamurthy Soumyanath; Gregory E. Dermer; Siva G. Narendra; Vivek De; Shekhar Borkar (IEEE J. Solid State Circuits, 2004)

Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS. - Siva G. Narendra; Vivek De; Shekhar Borkar; Dimitri A. Antoniadis; Anantha P. Chandrakasan (IEEE J. Solid State Circuits, 2004)

Low-voltage-swing monolithic dc-dc conversion. - Volkan Kursun; Siva G. Narendra; Vivek K. De; Eby G. Friedman (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

Cascode buffer for monolithic voltage conversion operating at high input supply voltages. - Volkan Kursun; Gerhard Schrom; Vivek De; Eby G. Friedman; Siva G. Narendra (ISCAS (1), 2005)

Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power. - James W. Tschanz; Siva G. Narendra; Ali Keshavarzi; Vivek De (ISCAS (1), 2005)

Challenges and design choices in nanoscale CMOS. - Siva G. Narendra (ACM J. Emerg. Technol. Comput. Syst., 2005)

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package. - Peter Hazucha; Gerhard Schrom; Jaehong Hahn; Bradley A. Bloechel; Paul Hack; Gregory E. Dermer; Siva G. Narendra; Donald S. Gardner; Tanay Karnik; Vivek De; Shekhar Borkar (IEEE J. Solid State Circuits, 2005)

Monolithic voltage conversion in low-voltage CMOS technologies. - Volkan Kursun; Vivek De; Eby G. Friedman; Siva G. Narendra (Microelectron. J., 2005)

TD: Trends in Wireless Systems. - Donhee Ham; Siva G. Narendra (ISSCC, 2007)

Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. - James W. Tschanz; Nam-Sung Kim; Saurabh Dighe; Jason Howard; Gregory Ruhl; Sriram R. Vangal; Siva G. Narendra; Yatin Hoskote; Howard Wilson; Carol Lam; Matthew Shuman; Carlos Tokunaga; et al. (ISSCC, 2007)

Carbon nanotube circuit design choices in the presence of metallic tubes. - Rehman Ashraf; Malgorzata Chrzanowska-Jeske; Siva G. Narendra (ISCAS, 2008)

Power Systems from the Gigawatt to the Microwatt - Generation, Distribution, Storage and Efficient Use of Energy (Forum). - Eugenio Cantatore; Siva G. Narendra (ISSCC, 2008)

Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference. - David Money Harris; Sreedhar Natarajan; Ram K. Krishnamurthy; Siva G. Narendra (IEEE J. Solid State Circuits, 2008)

Benefits and barriers for probabilistic design. - Siva G. Narendra (ASP-DAC, 2010)

Yield enhancement by tube redundancy in CNFET-based circuits. - Rehman Ashraf; Rajeev K. Nain; Malgorzata Chrzanowska-Jeske; Siva G. Narendra (ICECS, 2010)

The semiconductor industry in 2025. - Azeez Bhavnagarwala; Shekhar Borkar; Takayasu Sakurai; Siva G. Narendra (ISSCC, 2010)

Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes. - Rehman Ashraf; Rajeev K. Nain; Malgorzata Chrzanowska-Jeske; Siva G. Narendra (NANOARCH, 2010)

Performance analysis of CNFET based circuits in the presence of fabrication imperfections. - Malgorzata Chrzanowska-Jeske; Rehman Ashraf; Rajeev K. Nain; Siva G. Narendra (ISCAS, 2012)