A 16Gbps 3rd Order CTLE Design for Serial Links with High Channel Loss in 16nm FinFET. - Thota Pranay Kumar; Siva Kumar Rapina; Bheema Rao Nistala (VLSID, 2023)

Phase frequency detector with zero-reset pulse for low-spur Phase-locked loop applications. - Marichamy Divya; Siva Kumar Rapina; S. Kumaravel 001 (VLSID, 2024)

8GHz Multi-Phase Ring VCO Design with Wide Tuning Range for SerDes Applications in 6nm FinFET Process. - Ravuru Vasudeva Reddy; Siva Kumar Rapina; Siddhartha Hazra; K. Sarangam (VLSID, 2025)