Dynamic Mapping in a Heterogeneous Environment with Tasks Having Priorities and Multiple Deadlines. - Jong-Kook Kim; Sameer Shivle; Howard Jay Siegel; Anthony A. Maciejewski; Tracy D. Braun; Myron Schneider; Sonja Tideman; Ramakrishna Chitta; Raheleh B. Dilmaghani; Rohit Joshi; Aditya Kaul; Ashish Sharma; et al. (IPDPS, 2003)

ΔIDDQ Testing of a CMOS Digital-to-Analog Converter Considering Process Variation Effects. - Rajiv Soundararajan; Ashok Srivastava; Siva Sankar Yellampalli (Circuits Syst., 2011)

Design of power efficient SPI interface. - Dwaraka N. Oruganti; Siva Sankar Yellampalli (ICACCI, 2014)

The Design of Ultra Low Power CMOS CGLNA in Nanometer Technology. - P. Kavyashree; Siva Sankar Yellampalli (ISED, 2014)

Design and implementation of sample and hold circuit in 180nm CMOS technology. - Prakruthi T. G.; Siva Sankar Yellampalli (ICACCI, 2015)

Modified low power scan based technique. - M. R. Gowthami; G. Harish; B. V. Bhargav Ram; Siva Sankar Yellampalli (VDAT, 2015)

Low power and hardware cost STUMPS BIST. - N. Ravi Kiran; G. Harish; A. Karthik 004; Siva Sankar Yellampalli (VDAT, 2015)

Detection and analysis of hardware trojan using scan chain method. - Munishamanna Rithesh; G. Harish; B. V. Bhargav Ram; Siva Sankar Yellampalli (VDAT, 2015)

Analog BIST for Capacitive MEMS Sensor using PLL. - Favoureen Swer; V. Pradeep; Siva Sankar Yellampalli (WCI, 2015)

Smart Receivers with Modular and Multifunctional Front-End Blocks: The Benefits of Using Programmable Modulators and Demodulators. - Nanda Kishora Holla; Siva Sankar Yellampalli (IEEE Consumer Electron. Mag., 2019)

Smart Agriculture using IoT & Filtering Technology. - Sameeksha Konakalla; Lakshmi Vyshnavi Kunchala; Siva Sankar Yellampalli (ICCCNT, 2021)

Steep Switching NCFET based Logic for Future Energy Efficient Electronics. - Renuka Chowdary Bheemana; Aditya Japa; Siva Sankar Yellampalli; Ramesh Vaddi (iSES, 2021)

Systolic Array based Multiply Accumulation Unit for IoT Edge Accelerators. - P. L. Lahari; Siva Sankar Yellampalli; Ramesh Vaddi (iSES, 2021)

GPS and LoRa module Based Safety Alert system. - Parshal Chitrakar; Yoganand Biradavolu; Siva Sankar Yellampalli (RFID-TA, 2021)

Design and Exploration of Negative Capacitance FETs for Energy Efficient SRAM based In-Memory XNOR/Input and Weight Product Operation for Deep Neural Networks. - Venu Birudu; Siva Sankar Yellampalli; Ramesh Vaddi (iSES, 2022)

A Review of Various Defects in PCB. - V. Udaya Sankar; Gayathri Lakshmi; Y. Siva Sankar (J. Electron. Test., 2022)

Negative capacitance FETs for energy efficient and hardware secure logic designs. - Renuka Chowdary Bheemana; Aditya Japa; Siva Sankar Yellampalli; Ramesh Vaddi (Microelectron. J., 2022)

Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design. - Renuka Chowdary Bheemana; Aditya Japa; Siva Sankar Yellampalli; Ramesh Vaddi (Microelectron. J., 2023)

A negative capacitance FET based energy efficient 6T SRAM computing-in-memory (CiM) cell design for deep neural networks. - Venu Birudu; Siva Sankar Yellampalli; Ramesh Vaddi (Microelectron. J., 2023)

A Survey of PCB Defect Detection Algorithms. - Gayathri Lakshmi; V. Udaya Sankar; Y. Siva Sankar (J. Electron. Test., 2023)

Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices. - Venu Birudu; Tirumalarao Kadiyam; Koteswararao Penumalli; Aditya Japa; Sushma Nirmala Sambatur; Chongyan Gu; Siva Sankar Yellampalli; Ramesh Vaddi (ISCAS, 2024)

SyntDiaNet: Integrating feature extraction, transfer learning and classifier-embedded generative adversarial network for advanced pneumonia diagnosis. - Rahul Gowtham Poola; P. L. Lahari; Siva Sankar Yellampalli (Multim. Tools Appl., 2024)

RadiomixNet: Integrating Radiomics and Feature Extraction for Advanced Pneumonia Diagnosis. - Rahul Gowtham Poola; Siva Sankar Yellampalli (IEEE Access, 2025)