A High Performance and Full Utilization Hardware Implementation of Floating Point Arithmetic Units. - Chen Yang 018; Siwei Xiang; Jiaxing Wang; Liyan Liang (ICECS, 2021)

An Efficient Hardware Implementation of Dilated Convolution Using a Novel Channel-Equivalent Decomposition Method. - Yuheng Xia; Yishuo Meng; Siwei Xiang; Jianfei Wang 003; Chen Yang 005 (ICTA, 2023)

POSS-CNN: An Automatically Generated Convolutional Neural Network with Precision and Operation Separable Structure Aiming at Target Recognition and Detection. - Jia Hou; Jingyu Zhang; Qi Chen; Siwei Xiang; Yishuo Meng; Jianfei Wang 003; Cimang Lu; Chen Yang 005 (Inf., 2023)

An Efficient CNN Accelerator Achieving High PE Utilization Using a Dense-/Sparse-Aware Redundancy Reduction Method and Data-Index Decoupling Workflow. - Yishuo Meng; Chen Yang 005; Siwei Xiang; Jianfei Wang 003; Kuizhi Mei; Li Geng (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A High-Throughput and Flexible Architecture Based on a Reconfigurable Mixed-Radix FFT With Twiddle Factor Compression and Conflict-Free Access. - Chen Yang 005; Junfeng Wu; Siwei Xiang; Liyan Liang; Li Geng (IEEE Trans. Very Large Scale Integr. Syst., 2023)

A High-Throughput Toom-Cook-4 Polynomial Multiplier for Lattice-Based Cryptography Using a Novel Winograd-Schoolbook Algorithm. - Jianfei Wang 003; Chen Yang 005; Fahong Zhang 002; Yishuo Meng; Siwei Xiang; Yang Su 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

WRA-SS: A High-Performance Accelerator Integrating Winograd With Structured Sparsity for Convolutional Neural Networks. - Chen Yang 005; Yishuo Meng; Jiawei Xi; Siwei Xiang; Jianfei Wang 003; Kuizhi Mei (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Flexible and Efficient Convolutional Acceleration on Unified Hardware Using the Two-Stage Splitting Method and Layer-Adaptive Allocation of 1-D/2-D Winograd Units. - Chen Yang 005; Yaoyao Yang; Yishuo Meng; Kaibo Huo; Siwei Xiang; Jianfei Wang 003; Li Geng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A High-Throughput and Scalable Schoolbook Polynomial Multiplier for Accelerating Saber on FPGA Using a Novel Winograd-Based Architecture. - Jianfei Wang 003; Chen Yang 005; Fahong Zhang 002; Jia Hou; Yishuo Meng; Siwei Xiang; Yang Su 003 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

ALSCA: A Large-Scale Sparse CNN Accelerator Using Position-First Dataflow and Input Channel Merging Approach. - Yishuo Meng; Siwei Xiang; Jianfei Wang 003; Jia Hou; Chen Yang 005 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A High-Throughput and Flexible CNN Accelerator Based on Mixed-Radix FFT Method. - Yishuo Meng; Junfeng Wu; Siwei Xiang; Jianfei Wang 003; Jia Hou; Zhijie Lin; Chen Yang 005 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Reconfigurable and Area-Efficient Polynomial Multiplier Using a Novel In-Place Constant-Geometry NTT/INTT and Conflict-Free Memory Mapping Scheme. - Jianfei Wang 003; Chen Yang 005; Yishuo Meng; Fahong Zhang 002; Jia Hou; Siwei Xiang; Yang Su 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

Rethinking the Designing of Convolution Engine for Reconfigurable CNN Accelerator Using Sparse-Based Design Scheme. - Yishuo Meng; Jianfei Wang 003; Siwei Xiang; Jia Hou; Zhijie Lin; Kuizhi Mei; Chen Yang 005 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)