A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing. - Kai Li 024; Junzhuo Zhou; Boyu Li; Shuxing Yang; Sixiao Huang; Shaobo Luo; Wei Mao 002; Hao Yu 001 (AICAS, 2022)

A Vector Systolic Accelerator for Multi-Precision Floating-Point High-Performance Computing. - Kai Li 024; Wei Mao 002; Junzhuo Zhou; Boyu Li; Zhengke Yang; Shuxing Yang; Laimin Du; Sixiao Huang; Hao Yu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme. - Mingqiang Huang; Yucen Liu; Sixiao Huang; Kai Li 024; Qiuping Wu; Hao Yu 001 (FPGA, 2023)

An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge. - Mingqiang Huang; Junyi Luo; Chenchen Ding; Zikun Wei; Sixiao Huang; Hao Yu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

LAMPS: A Layer-wised Mixed-Precision-and-Sparsity Accelerator for NAS-Optimized CNNs on FPGA. - Shuxin Yang; Chenchen Ding; Mingqiang Huang; Kai Li 024; Chenghao Li 010; Zikun Wei; Sixiao Huang; Jingyao Dong; Liuyang Zhang; Hao Yu 001 (FCCM, 2024)

An MLA-LLM Hardware Acceleration with Tensor-Train Decomposition on Group Vector Systolic Accelerator. - Sixiao Huang; Tintin Wang; Keyao Jiang; Ao Shen; Kai Li; Ang Li; Mingqiang Huang; Hao Yu (ASAP, 2025)

A Tensor-Train Decomposition based Compression of LLMs on Group Vector Systolic Accelerator. - Sixiao Huang; Tintin Wang; Ang Li; Ao Shen; Kai Li; Keyao Jiang; Mingqiang Huang; Hao Yu (CoRR, 2025)