A carbon nanotube transistor based RISC-V processor using pass transistor logic. - Aporva Amarnath; Siying Feng; Subhankar Pal; Tutu Ajayi; Austin Rovinski; Ronald G. Dreslinski (ISLPED, 2017)

OuterSPACE: An Outer Product Based Sparse Matrix Multiplication Accelerator. - Subhankar Pal; Jonathan Beaumont; Dong-Hyeon Park; Aporva Amarnath; Siying Feng; Chaitali Chakrabarti; Hun-Seok Kim; David T. Blaauw; Trevor N. Mudge; Ronald G. Dreslinski (HPCA, 2018)

Parallelism Analysis of Prominent Desktop Applications: An 18- Year Perspective. - Siying Feng; Subhankar Pal; Yichen Yang 005; Ronald G. Dreslinski (ISPASS, 2019)

A 7.3 M Output Non-Zeros/J Sparse Matrix-Matrix Multiplication Accelerator using Memory Reconfiguration in 40 nm. - Subhankar Pal; Dong-Hyeon Park; Siying Feng; Paul Gao 001; Jielun Tan; Austin Rovinski; Shaolin Xie; Chun Zhao; Aporva Amarnath; Timothy Wesley; Jonathan Beaumont; Kuan-Yu Chen 001; et al. (VLSI Circuits, 2019)

Transmuter: Bridging the Efficiency Gap using Memory and Dataflow Reconfiguration. - Subhankar Pal; Siying Feng; Dong-Hyeon Park; Sung Kim; Aporva Amarnath; Chi-Sheng Yang; Xin He; Jonathan Beaumont; Kyle May; Yan Xiong 002; Kuba Kaszyk; John Magnus Morton; et al. (PACT, 2020)

Sparse-TPU: adapting systolic arrays for sparse matrices. - Xin He; Subhankar Pal; Aporva Amarnath; Siying Feng; Dong-Hyeon Park; Austin Rovinski; Haojie Ye; Kuan-Yu Chen 001; Ronald G. Dreslinski; Trevor N. Mudge (ICS, 2020)

HETSIM: Simulating Large-Scale Heterogeneous Systems using a Trace-driven, Synchronization and Dependency-Aware Framework. - Subhankar Pal; Kuba Kaszyk; Siying Feng; Björn Franke; Murray Cole; Michael F. P. O'Boyle; Trevor N. Mudge; Ronald G. Dreslinski (IISWC, 2020)

A 7.3 M Output Non-Zeros/J, 11.7 M Output Non-Zeros/GB Reconfigurable Sparse Matrix-Matrix Multiplication Accelerator. - Dong-Hyeon Park; Subhankar Pal; Siying Feng; Paul Gao 001; Jielun Tan; Austin Rovinski; Shaolin Xie; Chun Zhao; Aporva Amarnath; Timothy Wesley; Jonathan Beaumont; Kuan-Yu Chen 001; et al. (IEEE J. Solid State Circuits, 2020)

CoSPARSE: A Software and Hardware Reconfigurable SpMV Framework for Graph Analytics. - Siying Feng; Jiawen Sun; Subhankar Pal; Xin He; Kuba Kaszyk; Dong-Hyeon Park; John Magnus Morton; Trevor N. Mudge; Murray Cole; Michael F. P. O'Boyle; Chaitali Chakrabarti; Ronald G. Dreslinski (DAC, 2021)

SparseAdapt: Runtime Control for Sparse Linear Algebra on a Reconfigurable Accelerator. - Subhankar Pal; Aporva Amarnath; Siying Feng; Michael F. P. O'Boyle; Ronald G. Dreslinski; Christophe Dubach (MICRO, 2021)

Squaring the circle: Executing Sparse Matrix Computations on FlexTPU - A TPU-Like Processor. - Xin He; Kuan-Yu Chen 001; Siying Feng; Hun-Seok Kim; David T. Blaauw; Ronald G. Dreslinski; Trevor N. Mudge (PACT, 2022)

MeNDA: a near-memory multi-way merge solution for sparse transposition and dataflows. - Siying Feng; Xin He; Kuan-Yu Chen 001; Liu Ke 001; Xuan Zhang 001; David T. Blaauw; Trevor N. Mudge; Ronald G. Dreslinski (ISCA, 2022)

A 507 GMACs/J 256-Core Domain Adaptive Systolic-Array-Processor for Wireless Communication and Linear-Algebra Kernels in 12nm FINFET. - Kuan-Yu Chen 001; Chi-Sheng Yang; Yu-Hsiu Sun; Chien-Wei Tseng; Morteza Fayazi; Xin He; Siying Feng; Yufan Yue; Trevor N. Mudge; Ronald G. Dreslinski; Hun-Seok Kim; David T. Blaauw (VLSI Technology and Circuits, 2022)

Acceleration Techniques of Sparse Linear Algebra on Emerging Architectures - Siying Feng (2022)

Accelerating Graph Analytics on a Reconfigurable Architecture with a Data-Indirect Prefetcher. - Yichen Yang 005; Jingtao Li; Nishil Talati; Subhankar Pal; Siying Feng; Chaitali Chakrabarti; Trevor N. Mudge; Ronald G. Dreslinski (CoRR, 2023)

DAP: A 507-GMACs/J 256-Core Domain Adaptive Processor for Wireless Communication and Linear Algebra Kernels in 12-nm FINFET. - Kuan-Yu Chen 001; Chi-Sheng Yang; Yu-Hsiu Sun; Chien-Wei Tseng; Morteza Fayazi; Xin He; Siying Feng; Yufan Yue; Trevor N. Mudge; Ronald G. Dreslinski; Hun-Seok Kim; David T. Blaauw (IEEE J. Solid State Circuits, 2025)