Constructing Online Testable Circuits Using Reversible Logic. - Sk. Noor Mahammad; Kamakoti Veezhinathan (IEEE Trans. Instrum. Meas., 2010)

Hardware based genetic evolution of self-adaptive arbitrary response FIR filters. - Shoaib Mohammed; Sk. Noor Mahammad; V. Kamakoti 001 (Appl. Soft Comput., 2011)

Minimization of flow table for TCAM based openflow switches by virtual compression approach. - S. Veeramani; Manas Kumar; Sk. Noor Mahammad (IEEE ANTS, 2013)

Hybrid trie based partitioning of TCAM based openflow switches. - S. Veeramani; Manas Kumar; Sk. Noor Mahammad (IEEE ANTS, 2013)

Novel approach to secure channel using C-SCAN and microcontroller in openflow. - S. Veeramani; Biraja Nalini Rout; Sk. Noor Mahammad (IEEE ANTS, 2013)

Constructing scalable hierarchical switched openflow network using adaptive replacement of flow table management. - S. Veeramani; S. Rahul Sharma; Sk. Noor Mahammad (IEEE ANTS, 2013)

Memory Based Multiplier Design in Custom and FPGA Implementation. - M. Mohamed Asan Basiri; S. K. Noor Mahammad (ISI (1), 2014)

Hybrid Memetic Algorithm for FPGA Placement and Routing Using Parallel Genetic Tunneling. - Rajesh Eswarawaka; S. K. Noor Mahammad; B. Eswara Reddy (SocProS (2), 2014)

Efficient IP lookup using hybrid trie-based partitioning of TCAM-based open flow switches. - S. Veeramani; Sk. Noor Mahammad (Photonic Netw. Commun., 2014)

An Efficient Hardware-Based Higher Radix Floating Point MAC Design. - M. Mohamed Asan Basiri; Sk. Noor Mahammad (ACM Trans. Design Autom. Electr. Syst., 2014)

A novel adiabatic SRAM cell implementation using split level charge recovery logic. - S. Dinesh Kumar; S. K. Noor Mahammad (VDAT, 2015)

A Novel Ternary Content-Addressable Memory (TCAM) Design Using Reversible Logic. - S. Dinesh Kumar; Sk. Noor Mahammad (VLSID, 2015)

Genetic annealing with efficient strategies to improve the performance for the NP-hard and routing problems. - Rajesh Eswarawaka; S. K. Noor Mahammad; B. Eswara Reddy (J. Exp. Theor. Artif. Intell., 2015)

Configurable Folded IIR Filter Design. - M. Mohamed Asan Basiri; Sk. Noor Mahammad (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

An Efficient VLSI Architecture for Discrete Hadamard Transform. - M. Mohamed Asan Basiri; S. K. Noor Mahammad (VLSID, 2016)

Multi-mode parallel and folded VLSI architectures for 1D-fast Fourier transform. - M. Mohamed Asan Basiri; Sk. Noor Mahammad (Integr., 2016)

An efficient VLSI architecture for lifting based 1D/2D discrete wavelet transform. - M. Mohamed Asan Basiri; Sk. Noor Mahammad (Microprocess. Microsystems, 2016)

High speed multiplexer design using tree based decomposition algorithm. - M. Mohamed Asan Basiri; Sk. Noor Mahammad (Microelectron. J., 2016)

High Performance Integer DCT Architectures for HEVC. - M. Mohamed Asan Basiri; Sk. Noor Mahammad (VLSID, 2017)

A Novel Range Matching Architecture for Packet Classification Without Rule Expansion. - Shanmugakumar Murugesan; Sk. Noor Mahammad (ACM Trans. Design Autom. Electr. Syst., 2017)

An Efficient VLSI Architecture for Convolution Based DWT Using MAC. - M. Mohamed Asan Basiri; Sk. Noor Mahammad (VLSID, 2018)

A Novel Rule Mapping on TCAM for Power Efficient Packet Classification. - S. M. Srinivasavarma Vegesna; Ashok Chakravarthy Nara; Sk. Noor Mahammad (ACM Trans. Design Autom. Electr. Syst., 2019)

Discrete Orthogonal Multi-transform on Chip (DOMoC). - M. Mohamed Asan Basiri; Sk. Noor Mahammad (J. Signal Process. Syst., 2019)

Efficient implementation of mixed-precision multiply-accumulator unit for AI algorithms. - Chandana Mounica; Sagar Krishna; Sreehari Veeramachaneni; Sk. Noor Mahammad (Int. J. Circuit Theory Appl., 2020)

An Approach to Place Sink Node in a Wireless Sensor Network (WSN). - S. Veeramani; Sk. Noor Mahammad (Wirel. Pers. Commun., 2020)

Energy Efficient Approximate 4: 2 Compressors for Error Tolerant Applications. - L. Hemanth Krishna; J. Bhaskara Rao 001; Ayesha Sk; Sreehari Veeramachaneni; S. K. Noor Mahammad (ICECS, 2021)

Design and Analysis of Obfuscated Full Adders. - Sandeep Kolla; Ayesha Sk; Sreehari Veeramachaneni; Sk. Noor Mahammad (ICM, 2021)

Energy Efficient Approximate Multiplier Design for Image/Video Processing Applications. - L. Hemanth Krishna; J. Bhaskara Rao 001; Ayesha Sk; Sreehari Veeramachaneni; Sk. Noor Mahammad (iSES, 2021)

Energy Efficient and Multiplierless Approximate Integer DCT Implementation for HEVC. - S. Skandha Deepsita; Kuchipudi Divya; Sk. Noor Mahammad (VLSI-SoC, 2021)

Energy efficient signed and unsigned radix 16 booth multiplier design. - Y. Mounica; K. Naresh Kumar; Sreehari Veeramachaneni; S. K. Noor Mahammad (Comput. Electr. Eng., 2021)

Efficient design of 15: 4 counter using a novel 5: 3 counter for high-speed multiplication. - L. Hemanth Krishna; Neeharika M.; Vishvanath Janjirala; Sreehari Veeramachaneni; S. K. Noor Mahammad (IET Comput. Digit. Tech., 2021)

A TCAM-based Caching Architecture Framework for Packet Classification. - S. M. Srinivasavarma Vegesna; Shiv Vidhyut; Sk. Noor Mahammad (ACM Trans. Embed. Comput. Syst., 2021)

Fault Tolerant Technique for Processor Control Path to Mitigate SEUs in FPGA. - B. S. Chandrasekhar; S. Deepanjali; Sk. Noor Mahammad (iSES, 2022)

Logic Locking Designs at Transistor Level for Full Adders. - Sandeep Kolla; Ayesha Sk; Sreehari Veeramachaneni; Sk. Noor Mahammad (iSES, 2022)

Self Healing Controllers to Mitigate SEU in the Control Path of FPGA Based System: A Complete Intrinsic Evolutionary Approach. - S. Deepanjali; Sk. Noor Mahammad (J. Electron. Test., 2022)

A New Approximate 4-2 Compressor using Merged Sum and Carry. - Chinthalgiri Jyothi; Saranya Karunamurthi; Bhaskara Rao Jammu 001; Sreehari Veeramachaneni; Sk. Noor Mahammad (J. Electron. Test., 2022)

Low power, high speed approximate multiplier for error resilient applications. - S. Skandha Deepsita; Sk. Noor Mahammad (Integr., 2022)

Hardware-based multi-match packet classification in NIDS: an overview and novel extensions for improving the energy efficiency of TCAM-based classifiers. - S. M. Srinivasavarma Vegesna; Shanmukha Rao Pydi; Sk. Noor Mahammad (J. Supercomput., 2022)

Energy Efficient Error Resilient Multiplier Using Low-power Compressors. - S. Skandha Deepsita; Dhayala Kumar M; Sk. Noor Mahammad (ACM Trans. Design Autom. Electr. Syst., 2022)

A Perspective of IP Lookup Approach Using Graphical Processing Unit (GPU). - Veeramani Sonai; Indira Bharathi; Sk. Noor Mahammad (ICDCIT, 2023)

Energy efficient multiply-accumulate unit using novel recursive multiplication for error-tolerant applications. - S. Skandha Deepsita; T. Karthikeyan; Sk. Noor Mahammad (Integr., 2023)

Intrinsic Based Self-healing Adder Design Using Chromosome Reconstruction Algorithm. - Raghavendra Kumar Sakali; Sk. Noor Mahammad (J. Electron. Test., 2023)

Optimized Fault-Tolerant Adder Design Using Error Analysis. - Raghavendra Kumar Sakali; P. Balasubramanian; Ramesh Reddy; Sreehari Veeramachaneni; Sk. Noor Mahammad (J. Circuits Syst. Comput., 2023)

Deterministic Approach for Range-enhanced Reconfigurable Packet Classification Engine. - Dhayalakumar M; Sk. Noor Mahammad (ACM Trans. Reconfigurable Technol. Syst., 2023)

Preferential fault-tolerance multiplier design to mitigate soft errors in FPGAs. - Raghavendra Kumar Sakali; Sreehari Veeramachaneni; Sk. Noor Mahammad (Integr., 2023)

Fault-Tolerant Floating-Point Multiplier Design for Mission Critical Systems. - Raghavendra Kumar Sakali; Sreehari Veeramachaneni; Sk. Noor Mahammad (VLSID, 2024)

TeRa: Ternary and Range based packet classification engine. - Dhayalakumar M; Sk. Noor Mahammad (Integr., 2024)

Scalable and Accelerated Self-healing Control Circuit Using Evolvable Hardware. - S. Deepanjali; Sk. Noor Mahammad (ACM Trans. Design Autom. Electr. Syst., 2024)

A twofold bio-inspired system for mitigating SEUs in the controllers of digital system deployed on FPGA. - S. Deepanjali; S. K. Noor Mahammad (J. Supercomput., 2024)

Energy-Efficient Approximate Multiplier Design With Lesser Error Rate Using the Probability-Based Approximate 4:2 Compressor. - L. Hemanth Krishna; Ayesha Sk; J. Bhaskara Rao 001; Sreehari Veeramachaneni; Sk. Noor Mahammad (IEEE Embed. Syst. Lett., 2024)

Optimizing Multipliers: An Energy-Efficient Design Using a Novel 3: 2 Compressor. - L. Hemanth Krishna; Sreehari Veeramachaneni; Srinivasu Bodapati; Bhaskara Rao Jammu 001; Sk. Noor Mahammad (VLSID, 2025)

Energy efficient and high throughput prefix-based pattern matching technique on TCAMs for NIDS. - Sameera Shaik; S. M. Srinivasavarma Vegesna; Sk. Noor Mahammad (Integr., 2025)