Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSM. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski (Int. J. Appl. Math. Comput. Sci., 2007)

Hardware reduction for FSM - Based control units using PAL technology. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski (EWDTS, 2010)

Reduction in the number of PAL macrocells for Moore FSM implemented with CPLD. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski (EWDTS, 2010)

Synthesis of control unit with refined state encoding for CPLD devices. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski (EWDTS, 2011)

Synthesis of Moore Finite State Machines Based on Pseudoequivalent States. - Alexander Barkalov 001; Slawomir Chmielewski; Larysa Titarenko (PDeS, 2013)

Hardware Reduction in CPLD-Based Moore FSM. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski (J. Circuits Syst. Comput., 2014)

Design of FPGA-based Mealy FSMs with Counters. - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek; Slawomir Chmielewski (MIXDES, 2018)

Design of CPLD-based mealy FSMs with counters. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski (MOCAST, 2018)

Mixed Encoding of Collections of Output Variables for LUT-Based Mealy FSMs. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski (J. Circuits Syst. Comput., 2019)

Improving Characteristics of LUT-Based Moore FSMs. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski (IEEE Access, 2020)

Logic Synthesis for FPGA-Based Control Units - Structural Decomposition in Logic Design - Alexander Barkalov 001; Larysa Titarenko; Kamil Mielcarek; Slawomir Chmielewski (Springer, 2020)

Improving Characteristics of FSMs With Mixed Codes of Outputs. - Alexander Barkalov 001; Larysa Titarenko; Slawomir Chmielewski; Kamil Mielcarek (IEEE Access, 2022)