Assessing the Impact of Temperature and Supply Voltage Variations in Near-threshold Circuits using an Analytical Model. - Sneh Saurabh; Vishav Vikash (ACM Great Lakes Symposium on VLSI, 2018)

A Practical Methodology to Compress Technology Libraries Using Recursive Polynomial Representation. - Sneh Saurabh; Priyanka Mittal (VLSID, 2018)

Application of Probabilistic Spin Logic (PSL) in Detecting Satisfiability of a Boolean Function. - Vaibhav Agarwal; Sneh Saurabh (ISQED, 2019)

Realizing Boolean Functions Using Probabilistic Spin Logic (PSL). - Vaibhav Agarwal; Sneh Saurabh (VLSID, 2019)

Implementing Logic Functions Using Independently-Controlled Gate in Double-Gate Tunnel FETs: Investigation and Analysis. - Shelly Garg; Sneh Saurabh (IEEE Access, 2019)

Dopingless 1T DRAM: Proposal, Design, and Analysis. - Akhil James; Sneh Saurabh (IEEE Access, 2019)

Suppression of Ambipolar current in Tunnel Field-Effect Transistor using Field-Plate. - Subhadip Poria; Shelly Garg; Sneh Saurabh (VDAT, 2020)

An Efficient Timing Model of Flip-Flops Based on Artificial Neural Network. - Madhvi Agarwal; Sneh Saurabh (MLCAD, 2021)

Reducing Breakdown Voltage in a Bipolar Impact Ionization MOSFET (BI-MOS) using Gate-Source Underlap. - Akshay Balaji; Sneh Saurabh (VLSI-SoC, 2021)

Effect of Drain Induced Barrier Enhancement on Subthreshold Swing and OFF-State Current of Short Channel MOSFETs: A TCAD Study. - Mamidala Karthik Ram; Neha Tiwari; Dawit Burusie Abdi; Sneh Saurabh (IEEE Access, 2021)

Drain Induced Barrier Widening and Reverse Short Channel Effects in Tunneling FETs: Investigation and Analysis. - Mamidala Karthik Ram; Neha Tiwari; Dawit Burusie Abdi; Sneh Saurabh (IEEE Access, 2021)

Modeling Multiple-Input Switching in Timing Analysis Using Machine Learning. - O. V. S. Shashank Ram; Sneh Saurabh (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Comparison of SAT-based and SMT-based Frameworks for X-value Combinational Equivalence Checking. - Raiyyan Malik; Shubham Baunthiyal; Puneet Kumar; Srinath J; Sneh Saurabh (VLSI-SoC, 2022)

Image Completion using a Sparse Probabilistic Spin Logic Network. - Amina Haroon; Sneh Saurabh (VLSID, 2022)

Deep Neural Network Augmented Wireless Channel Estimation on System on Chip. - Syed Asrar ul Haq; Abdul Karim Gizzini; Shakti Shrey; Sumit Jagdish Darak; Sneh Saurabh; Marwa Chafii (CoRR, 2022)

Muller C-Element Exploiting Programmable Metallization Cell for Bayesian Inference. - Jasmine Kaur; Sneh Saurabh; Shubham Sahay (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

Characterization Data for Flip-flop. - Sneh Saurabh; Rajat Kumar (IEEE DataPort, 2022)

Implementation of Probabilistic Bits (Pbits) using Low Barrier Magnets: Investigation and Analysis. - Amina Haroon; Ram Krishna Ghosh; Sneh Saurabh (VLSID, 2023)

Deep Neural Network Augmented Wireless Channel Estimation for Preamble-Based OFDM PHY on Zynq System on Chip. - Syed Asrar ul Haq; Abdul Karim Gizzini; Shakti Shrey; Sumit Jagdish Darak; Sneh Saurabh; Marwa Chafii (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Artificial Neural Network-based Prediction and Alleviation of Congestion during Placement. - Pooja Beniwal; Sneh Saurabh (VLSID, 2024)

FLIP: An Artificial Neural Network-based Post-routing Incremental Placer. - Pranav Jain; Gagandeep; Sneh Saurabh (VLSID, 2024)

Improving Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis. - Shivendra Singh; Ekta Tiwari; Abhinav Gupta; Sneh Saurabh (VLSID, 2024)

Impact of Non-Idealities on the Behavior of Probabilistic Computing: Theoretical Investigation and Analysis. - Amina Haroon; Ram Krishna Ghosh; Sneh Saurabh (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)