Novel reconfigurable two-MOSFET UV-programmable floating-gate circuits for CARRY, NAND, NOR or INVERT functions. - Snorre Aunet; Yngvar Berg; Øivind Næss; Trond Sæther (ICECS, 2001)

A method for simulation of floating-gate UV-programmable circuits with application to three new 2-MOSFET digital circuits. - Snorre Aunet; Yngvar Berg; Trond Ytterdal; Øivind Næss; Trond Sæther (ICECS, 2001)

A 0.3 V floating-gate differential amplifier input stage with tunable gain. - Yngvar Berg; Snorre Aunet; Øivind Næss; Henning Gundersen; Mats Høvin (ICECS, 2001)

A novel low-voltage floating-gate CMOS transconductance amplifier with sinh (tanh) shaped output current. - Yngvar Berg; Snorre Aunet; Øivind Næss; Mats Høvin (ICECS, 2001)

Extreme low-voltage floating-gate CMOS transconductance amplifier. - Yngvar Berg; Snorre Aunet; Øivind Næss; Henning Gundersen; Mats Høvin (ISCAS (1), 2001)

Floating-gate CMOS differential analog inverter for ultra low-voltage applications. - Yngvar Berg; Snorre Aunet; Øivind Næss; Mats Høvin (ISCAS (1), 2001)

Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion. - Yngvar Berg; Snorre Aunet; Øivind Næss; Mats Høvin (ISCAS (4), 2001)

A novel floating-gate multiple-valued signal to binary signal converter. - Yngvar Berg; Øivind Næss; Snorre Aunet; Mats Høvin (ICECS, 2002)

A novel floating-gate binary signal to multiple-valued signal converter for multiple-valued CMOS logic. - Yngvar Berg; Øivind Næss; Snorre Aunet; Johannes Goplen Lomsdalen; Mats Høvin (ICECS, 2002)

A novel floating-gate multiple-valued CMOS full-adder. - Yngvar Berg; Snorre Aunet; Øivind Næss; O. Hagen; Mats Høvin (ISCAS (1), 2002)

Novel floating-gate multiple-valued signal to binary signal converters for multiple-valued CMOS logic. - Yngvar Berg; Øivind Næss; Snorre Aunet; Renè Jensen; Mats Høvin (ISCAS (5), 2002)

Compact low-voltage self-calibrating digital floating-gate CMOS logic circuits. - Trond Ytterdal; Snorre Aunet (ISCAS (5), 2002)

Real-Time Reconfigurable Linear Threshold Elements and Some Applications to Neural Hardware. - Snorre Aunet; Morten Hartmann (ICES, 2003)

Novel recharge semi-floating-gate CMOS logic for multiple-valued systems. - Yngvar Berg; Snorre Aunet; Omid Mirmotahari; Mats Høvin (ISCAS (5), 2003)

Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers. - Yngvar Berg; Snorre Aunet; Øivind Næss; Johannes Goplen Lomsdalen; Mats Høvin (ISCAS (1), 2003)

UV-programmable Floating-Gate CMOS Linear Threshold Element "P1N3". - Snorre Aunet; Yngvar Berg (IWANN (2), 2003)

Real-time reconfigurable linear threshold elements implemented in floating-gate CMOS. - Snorre Aunet; Yngvar Berg; Trond Sæther (IEEE Trans. Neural Networks, 2003)

Erratum to "real-time reconfigurable linear threshold elements implemented in floating-gate CMOS". - Snorre Aunet; Yngvar Berg; Trond Sæther (IEEE Trans. Neural Networks, 2003)

Reconfigurable subthreshold CMOS perceptron. - Snorre Aunet; Bengt Oelmann; Suliman Abdalla; Yngvar Berg (IJCNN, 2004)

Basic Multiple-Valued Functions Using Recharge CMOS Logic. - Yngvar Berg; Snorre Aunet; Øivind Næss; Omid Mirmotahari (ISMVL, 2004)

On the Advantages of Serial Architectures for Low-Power Reliable Computations. - Valeriu Beiu; Snorre Aunet; Jabulani Nyathi; Ray Robert Rydberg III; Asbjørn Djupdal (ASAP, 2005)

Ultra low power fault tolerant neural inspired CMOS logic. - Snorre Aunet; Valeriu Beiu (IJCNN, 2005)

Low-voltage pseudo floating-gate reconfigurable linear threshold elements. - Øivind Næss; Snorre Aunet; Yngvar Berg (IJCNN, 2005)

Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures. - Valeriu Beiu; Asbjørn Djupdal; Snorre Aunet (IWANN, 2005)

Using Kolmogorov Inspired Gates for Low Power Nanoelectronics. - Valeriu Beiu; Artur Zawadski; Razvan Andonie; Snorre Aunet (IWANN, 2005)

Femto Joule Switching for Nano Electronics. - Valeriu Beiu; Jabulani Nyathi; Snorre Aunet; Mawahib H. Sulieman (AICCSA, 2006)

Six Subthreshold Full Adder Cells Characterized in 90 nm CMOS Technology. - Kristian Granhaug; Snorre Aunet (DDECS, 2006)

Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates. - Kristian Granhaug; Snorre Aunet (DFT, 2006)

Ultra low voltage CMOS gates. - Yngvar Berg; Omid Mirmotahari; Per Andreas Norseng; Snorre Aunet (ICECS, 2006)

Body-bias regulator for ultra low power multifunction CMOS gates. - Kristian Granhaug; Snorre Aunet; Tor Sverre Lande (ISCAS, 2006)

Pseudo Floating-Gate Inverter with Feedback Control. - Yngvar Berg; Omid Mirmotahari; Snorre Aunet (VLSI-SoC, 2006)

Band Pass Pseudo Floating-Gate Amplifier. - Yngvar Berg; Mehdi Azadmehr; Omid Mirmotahari; Snorre Aunet (ICECS, 2007)

Fault Tolerant CMOS Logic Using Ternary Gates. - Yngvar Berg; Renè Jensen; Johannes Goplen Lomsdalen; Henning Gundersen; Snorre Aunet (ISMVL, 2007)

Statistical Simulations for Exploring Defect Tolerance and Power Consumption for 4 Subthreshold 1-Bit Addition Circuits. - Snorre Aunet; Hans Kristian Otnes Berge (IWANN, 2007)

Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply. - Jon Alfredsson; Snorre Aunet (PATMOS, 2007)

Small Fan-in Floating-Gate Circuits with Application to an Improved Adder Structure. - Jon Alfredsson; Snorre Aunet; Bengt Oelmann (VLSI Design, 2007)

Serial Addition: Locally Connected Architectures. - Valeriu Beiu; Snorre Aunet; Jabulani Nyathi; Ray Robert Rydberg III; Walid Ibrahim (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology. - Håvard Pedersen Alstad; Snorre Aunet (DDECS, 2008)

Improving Circuit Security against Power Analysis Attacks with Subthreshold Operation. - Håvard Pedersen Alstad; Snorre Aunet (DDECS, 2008)

High speed and ultra low voltage CMOS latch. - Yngvar Berg; Omid Mirmotahari; Snorre Aunet (ICECS, 2008)

Ultra low voltage and, nor and XOR CMOS gates. - Yngvar Berg; Omid Mirmotahari; Snorre Aunet (ICECS, 2008)

Clocked semi-floating-gate ultra low-voltage current mirror. - Yngvar Berg; Omid Mirmotahari; Snorre Aunet (ICECS, 2008)

High Speed Ultra Low Voltage CMOS inverter. - Yngvar Berg; Omid Mirmotahari; Johannes Goplen Lomsdalen; Snorre Aunet (ISVLSI, 2008)

65NM sub-threshold 11T-SRAM for ultra low voltage applications. - Farshad Moradi; Dag T. Wisland; Snorre Aunet; Hamid Mahmoodi; Tuan Vu Cao (SoCC, 2008)

Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy. - Kristian Granhaug; Snorre Aunet (J. Electron. Test., 2008)

Real-Time Reconfigurable Subthreshold CMOS Perceptron. - Snorre Aunet; Bengt Oelmann; Per Andreas Norseng; Yngvar Berg (IEEE Trans. Neural Networks, 2008)

Ultra Low Power Full Adder Topologies. - Farshad Moradi; Dag T. Wisland; Hamid Mahmoodi; Snorre Aunet; Tuan Vu Cao; Ali Peiravi (ISCAS, 2009)

New subthreshold concepts in 65nm CMOS technology. - Farshad Moradi; Dag T. Wisland; Hamid Mahmoodi; Ali Peiravi; Snorre Aunet; Tuan Vu Cao (ISQED, 2009)

Synthetic Neuron Implementations. - Snorre Aunet (Encyclopedia of Artificial Intelligence, 2009)

Statistical Simulations on Perceptron-Based Adders. - Snorre Aunet; Hans Kristian Otnes Berge (Encyclopedia of Artificial Intelligence, 2009)

Memory elements based on minority-3 gates and inverters implemented in 90 nm CMOS. - Snorre Aunet; Amir Hasanbegovic (DDECS, 2010)

Design of 9T SRAM for dynamic voltage supplies by a multiobjective optimization approach. - Hans Kristian Otnes Berge; Matthias W. Blesken; Snorre Aunet; Ulrich Rückert 001 (ICECS, 2010)

Muller C-elements based on minority-3 functions for ultra low voltage supplies. - Hans Kristian Otnes Berge; Amir Hasanbegovic; Snorre Aunet (DDECS, 2011)

On the reliability of ultra low voltage circuits built from minority-3 gates. - Snorre Aunet (ECCTD, 2011)

Multi-objective optimization of minority-3 functions for ultra-low voltage supplies. - Hans Kristian Otnes Berge; Snorre Aunet (ISCAS, 2011)

Low-power subthreshold to above threshold level shifters in 90 nm and 65 nm process. - Amir Hasanbegovic; Snorre Aunet (Microprocess. Microsystems, 2011)

A 9-bit 50MS/s asynchronous SAR ADC in 28nm CMOS. - Tuan Vu Cao; Snorre Aunet; Trond Ytterdal (NORCHIP, 2012)

Yield-oriented energy and performance model for subthreshold circuits with Vth variations. - Hans Kristian Otnes Berge; Snorre Aunet (DDECS, 2013)

Proton beam characterization at Oslo Cyclotron Laboratory for radiation testing of electronic devices. - Amir Hasanbegovic; Snorre Aunet (DDECS, 2013)

A 65 nm 32 b Subthreshold Processor With 9T Multi-Vt SRAM and Adaptive Supply Voltage Control. - Sven Lütkemeier; Thorsten Jungeblut; Hans Kristian Otnes Berge; Snorre Aunet; Mario Porrmann; Ulrich Rückert 001 (IEEE J. Solid State Circuits, 2013)

Modular layout-friendly cell library design applied for subthreshold CMOS. - Jonathan Edvard Bjerkedok; Ali Asghar Vatanjou; Trond Ytterdal; Snorre Aunet (NORCHIP, 2014)

Performance comparison of 5 subthreshold CMOS flip-flops under process-, voltage-, and temperature variations, based on netlists from layout. - Magne Voernes; Trond Ytterdal; Snorre Aunet (NORCHIP, 2014)

Exploiting short channel effects and multi-Vt technology for increased robustness and reduced energy consumption, with application to a 16-bit subthreshold adder implemented in 65 nm CMOS. - Ali Asghar Vatanjou; Trond Ytterdal; Snorre Aunet (ECCTD, 2015)

4 Sub-/near-threshold flip-flops with application to frequency dividers. - Ali Asghar Vatanjou; Trond Ytterdal; Snorre Aunet (ECCTD, 2015)

An ultra-low-power/high-speed 9-bit adder design: Analysis and comparison Vs. technology from 130nm-LP to UTBB FD-SOI-28nm. - Hourieh Attarzadeh; Snorre Aunet; Trond Ytterdal (NORCAS, 2015)

Comparative analysis of flip-flop architectures for subthreshold applications in 28nm FDSOI. - Even Låte; Ali Asghar Vatanjou; Trond Ytterdal; Snorre Aunet (NORCAS, 2015)

28 nm UTBB-FDSOI energy efficient and variation tolerant custom digital-cell library with application to a subthreshold MAC block. - Ali Asghar Vatanjou; Trond Ytterdal; Snorre Aunet (MIXDES, 2016)

Ultra-low voltage adders in 28 nm FDSOI exploring poly-biasing for device sizing. - Ali Asghar Vatanjou; Even Låte; Trond Ytterdal; Snorre Aunet (NORCAS, 2016)

Extended Comparative Analysis of Flip-Flop Architectures for Subthreshold Applications in 28 nm FD-SOI. - Even Låte; Ali Asghar Vatanjou; Trond Ytterdal; Snorre Aunet (Microprocess. Microsystems, 2017)

Special issue: Selected papers from the 1st NORCAS conference (2015 Nordic Circuits and Systems Conference (NORCAS): Norchip & International Symposium on System-on-Chip (SoC)). - Jim Tørresen; Snorre Aunet (Microprocess. Microsystems, 2017)

Comparison of Ultra Low Power Full Adder Cells in 22 nm FDSOI Technology. - Somayeh Hossein Zadeh; Trond Ytterdal; Snorre Aunet (NORCAS, 2018)

A loadless 6T SRAM cell for sub- & near- threshold operation implemented in 28 nm FD-SOI CMOS technology. - Even Låte; Trond Ytterdal; Snorre Aunet (Integr., 2018)

Ultra-low voltage and energy efficient adders in 28 nm FDSOI exploring poly-biasing for device sizing. - Ali Asghar Vatanjou; Even Låte; Trond Ytterdal; Snorre Aunet (Microprocess. Microsystems, 2018)

A Configurable and Versatile Architecture for Low Power, Energy Efficient Hardware Acceleration of Convolutional Neural Networks. - Steinar Thune Christensen; Snorre Aunet; Omer Qadir (NORCAS, 2019)

Nwise: an Area Efficient and Highly Reliable Radiation Hardened Memory Cell Designed for Space Applications. - Azam Seyedi; Snorre Aunet; Per Gunnar Kjeldsberg (NORCAS, 2019)

Ultra-Low Voltage Subthreshold Binary Adder Architectures for IoT Applications: Ripple Carry Adder or Kogge Stone Adder. - Somayeh Hossein Zadeh; Trond Ytterdal; Snorre Aunet (NORCAS, 2019)

Exploring optimal back bias voltages for ultra low voltage CMOS digital Circuits in 22 nm FDSOI Technology. - Somayeh Hossein Zadeh; Trond Ytterdal; Snorre Aunet (NORCAS, 2019)

An Ultra-Low Voltage and Low-Energy Level Shifter in 28-nm UTBB-FDSOI. - Ali Asghar Vatanjou; Trond Ytterdal; Snorre Aunet (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Comparative Study of Single, Regular and Flip Well Subthreshold SRAMs in 22 nm FDSOI Technology. - Somayeh Hossein Zadeh; Trond Ytterdal; Snorre Aunet (NorCAS, 2020)

Multi-threshold Voltage and Dynamic Body Biasing Techniques for Energy Efficient Ultra Low Voltage Subthreshold Adders. - Somayeh Hossein Zadeh; Trond Ytterdal; Snorre Aunet (NorCAS, 2020)

An Energy Efficient Level Shifter Capable of Logic Conversion From Sub-15 mV to 1.2 V. - Even Låte; Trond Ytterdal; Snorre Aunet (IEEE Trans. Circuits Syst., 2020)

Benefiting From State Dependencies in Asymmetric SRAM Cells Through Conditional Word-Flipping. - Even Låte; Trond Ytterdal; Snorre Aunet (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Ultra Low Voltage Sub-100 mV Vdd CMOS. - Snorre Aunet (NEWCAS, 2021)

Subthreshold Power PC and Nand Race-Free Flip-Flops in Frequency Divider Applications. - Somayeh Hossein Zadeh; Trond Ytterdal; Snorre Aunet (NorCAS, 2021)

Fast and Accurate Edge Computing Energy Modeling and DVFS Implementation in GEM5 Using System Call Emulation Mode. - Yahya H. Yassin; Magnus Jahre; Per Gunnar Kjeldsberg; Snorre Aunet; Francky Catthoor (J. Signal Process. Syst., 2021)

Nwise and Pwise: 10T Radiation Hardened SRAM Cells for Space Applications With High Reliability Requirements. - Azam Seyedi; Snorre Aunet; Per Gunnar Kjeldsberg (IEEE Access, 2022)

Randomized Bulk-Voltages: A Countermeasure to Mask Side-Channel Leakage of CMOS Logic Gates. - Magnus Amble; Snorre Aunet; Dag T. Wisland; Kristian Gjertsen Kjelgård (MWSCAS, 2023)

Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2022. - Jari Nurmi; Snorre Aunet; Alireza Saberkari (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Guest Editorial Selected Papers From IEEE Nordic Circuits and Systems Conference (NorCAS) 2023. - Jari Nurmi; Snorre Aunet; Alireza Saberkari (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Optimizing Energy Efficiency in Subthreshold RISC-V Cores. - Asbjørn Djupdal; Magnus Själander; Magnus Jahre; Snorre Aunet; Trond Ytterdal (CoRR, 2025)