A 4nm 16Gb/s/pin Single-Ended PAM4 Parallel Transceiver with Switching-Jitter Compensation and Transmitter Optimization. - Jahoon Jin; Soo-Min Lee; Kyunghwan Min; Sodam Ju; Jihoon Lim; Hyunsu Chae; Kwonwoo Kang; Yunji Hong; Yeongcheol Jeong; Sang-Ho Kim; Jongwoo Lee; Joonsuk Kim (ISSCC, 2023)

A 20Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing for Low-Power Memory Interfaces. - Kyunghwan Min; Jahoon Jin; Soo-Min Lee; Sodam Ju; Jisu Yook; Jihoon Lee; Yunji Hong; Sungsik Park; Sang-Ho Kim; Jongwoo Lee; Hyungjong Ko (VLSI Technology and Circuits, 2024)

A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization. - Jahoon Jin; Soo-Min Lee; Kyunghwan Min; Sodam Ju; Jihoon Lim; Jisu Yook; Jihoon Lee; Hyunsu Chae; Kwonwoo Kang; Yunji Hong; Yeongcheol Jeong; Sungsik Park; et al. (IEEE J. Solid State Circuits, 2024)