Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices. - Sohan Purohit; Sai Rahul Chalamalasetti; Martin Margala; Pasquale Corsonello (ReConFig, 2008)

Power/throughput/area efficient PIM-based reconfigurable array for parallel processing. - Sohan Purohit; Sai Rahul Chalamalasetti; Martin Margala; Pasquale Corsonello (SoCC, 2008)

MORA - An Architecture and Programming Model for a Resource Efficient Coarse Grained Reconfigurable Processor. - Sai Rahul Chalamalasetti; Sohan Purohit; Martin Margala; Wim Vanderbauwhede (AHS, 2009)

Programming Model and Low-level Language for a Coarse-Grained Reconfigurable Multimedia Processor. - Wim Vanderbauwhede; Martin Margala; Sai Rahul Chalamalasetti; Sohan Purohit (ERSA, 2009)

A low cost reconfigurable soft processor for multimedia applications: Design synthesis and programming model. - Sai Rahul Chalamalasetti; Wim Vanderbauwhede; Sohan Purohit; Martin Margala (FPL, 2009)

A 1.2v, 1.02 ghz 8 bit SIMD compatible highly parallel arithmetic data path for multi-precision arithmetic. - Sohan Purohit; Sai Rahul Chalamalasetti; Martin Margala (ACM Great Lakes Symposium on VLSI, 2009)

New performance/power/area efficient, reliable full adder design. - Sohan Purohit; Martin Margala; Marco Lanuzza; Pasquale Corsonello (ACM Great Lakes Symposium on VLSI, 2009)

Design-Space Exploration of Energy-Delay-Area Efficient Coarse-Grain Reconfigurable Datapath. - Sohan Purohit; Marco Lanuzza; Stefania Perri; Pasquale Corsonello; Martin Margala (VLSI Design, 2009)

Design and Evaluation of an Energy-Delay-Area Efficient Datapath for Coarse-Grain Reconfigurable Computing Systems. - Sohan Purohit; Marco Lanuzza; Stefania Perri; Pasquale Corsonello; Martin Margala (J. Low Power Electron., 2009)

Performance and area efficient transpose memory architecture for high throughput adaptive signal processing systems. - Mohamed El-Hadedy 001; Sohan Purohit; Martin Margala; Svein J. Knapskog (AHS, 2010)

Low overhead soft error detection and correction scheme for reconfigurable pipelined data paths. - Sohan Purohit; Sai Rahul Chalamalasetti; Martin Margala (AHS, 2010)

A C++-embedded Domain-Specific Language for programming the MORA soft processor array. - Wim Vanderbauwhede; Martin Margala; Sai Rahul Chalamalasetti; Sohan Purohit (ASAP, 2010)

Design of self correcting radiation hardened digital circuits using decoupled ground bus. - Sohan Purohit; Sai Rahul Chalamalasetti; Martin Margala (ACM Great Lakes Symposium on VLSI, 2010)

An area efficient design methodology for SEU tolerant digital circuits. - Sohan Purohit; David Harrington; Martin Margala (ISCAS, 2010)

Radiation-Hardened Reconfigurable Array With Instruction Roll-Back. - Sai Rahul Chalamalasetti; Sohan Purohit; Martin Margala; Wim Vanderbauwhede (IEEE Embed. Syst. Lett., 2010)

Design Space Exploration of Split-Path Data Driven Dynamic Full Adder. - Sohan Purohit; Marco Lanuzza; Martin Margala (J. Low Power Electron., 2010)

A few lines of code, thousands of cores: High-level FPGA programming using vector processor networks. - Wim Vanderbauwhede; Sai Rahul Chalamalasetti; Sohan Purohit; Martin Margala (HPCS, 2011)

Investigating the Impact of Logic and Circuit Implementation on Full Adder Performance. - Sohan Purohit; Martin Margala (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Throughput/Resource-Efficient Reconfigurable Processor for Multimedia Applications. - Sohan Purohit; Sai Rahul Chalamalasetti; Martin Margala; Wim Vanderbauwhede (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Design and Evaluation of High-Performance Processing Elements for Reconfigurable Systems. - Sohan Purohit; Sai Rahul Chalamalasetti; Martin Margala; Wim Vanderbauwhede (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Designing Dynamic Carry Skip Adders: Analysis and Comparison. - Raffaele De Rose; Marco Lanuzza; Fabio Frustaci; Sohan Purohit (Circuits Syst. Signal Process., 2014)