A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications. - Hui Xu; Jun Tanabe; Hiroyuki Usui; Soichiro Hosoda; Toru Sano; Kazumasa Yamamoto; Takeshi Kodaka; Nobuhiro Nonogaki; Nau Ozaki; Takashi Miyamori (VLSIC, 2012)

Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters. - Takashi Miyamori; Hui Xu; Hiroyuki Usui; Soichiro Hosoda; Toru Sano; Kazumasa Yamamoto; Takeshi Kodaka; Nobuhiro Nonogaki; Nau Ozaki; Jun Tanabe (IEICE Trans. Electron., 2014)

A 20.5TOPS and 217.3GOPS/mm2 Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications. - Yutaka Yamada; Toru Sano; Yasuki Tanabe; Yutaro Ishigaki; Soichiro Hosoda; Fumihiko Hyuga; Akira Moriya; Ryuji Hada; Atsushi Masuda; Masato Uchiyama; Tomohiro Koizumi; Takanori Tamai; et al. (ISSCC, 2019)

A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications. - Yutaka Yamada; Masato Uchiyama; Masashi Jobashi; Tomohiro Koizumi; Takanori Tamai; Nobuhiro Sato; Jun Tanabe; Katsuyuki Kimura; Yoshinari Ojima; Ryusuke Murakami; Takashi Yoshikawa; Toru Sano; et al. (IEEE J. Solid State Circuits, 2020)