Modified reduced delay BCD adder. - C. Sundaresan; C. V. S. Chaitanya; P. R. Venkateswaran; Somashekara Bhat; J. Mohan Kumar (BMEI, 2011)

Load Cell and FSR-Based Hand-Assistive Device. - K. Aneesha Acharya; Somashekara Bhat; M. Kanthi (ICACIE (1), 2019)

Accelerometer based quantitative outcome measurement for hand function test. - K. Aneesha Acharya; Somashekara Bhat; M. Kanthi (Int. J. Sens. Networks, 2019)

A Novel Low Power and Reduced Transistor Count Magnetic Arithmetic Logic Unit Using Hybrid STT-MTJ/CMOS Circuit. - Prashanth Barla; Vinod Kumar Joshi; Somashekara Bhat (IEEE Access, 2020)

From MTJ Device to Hybrid CMOS/MTJ Circuits: A Review. - Vinod Kumar Joshi; Prashanth Barla; Somashekara Bhat; Brajesh Kumar Kaushik (IEEE Access, 2020)

Design and Evaluation of a Self Write-Terminated Hybrid MTJ/CMOS Full Adder Based on LIM Structure. - Prashanth Barla; Vinod Kumar Joshi; Somashekara Bhat (J. Circuits Syst. Comput., 2022)