A scalable hybrid verification system based on HDL slicing. - Somnath Banerjee 003; Tushar Gupta; Saurabh Jain (HLDVT, 2011)

Fast and scalable hybrid functional verification and debug with dynamically reconfigurable co-simulation. - Somnath Banerjee 003; Tushar Gupta (ICCAD, 2012)

Efficient Online RTL Debugging Methodology for Logic Emulation Systems. - Somnath Banerjee 003; Tushar Gupta (VLSI Design, 2012)

Optimized Simulation Acceleration with Partial Testbench Evaluation. - Somnath Banerjee 003; Tushar Gupta (MTV, 2014)