Hardware/Software Co-design of a High-end Mixed Signal Microcontroller. - Pradeep K. Mishra; Somnath Paul; S. Venkataraman; Rajat Gupta (VLSI Design, 1998)

Low-overhead design technique for calibration of maximum frequency at multiple operating points. - Somnath Paul; Sivasubramaniam Krishnamurthy; Hamid Mahmoodi; Swarup Bhunia (ICCAD, 2007)

Memory based computation using embedded cache for processor yield and reliability improvement. - Somnath Paul; Swarup Bhunia (ICCD, 2007)

Defect-Aware Configurable Computing in Nanoscale Crossbar for Improved Yield. - Somnath Paul; Rajat Subhra Chakraborty; Swarup Bhunia (IOLTS, 2007)

Adaptation to Temperature-Induced Delay Variations in Logic Circuits Using Low-Overhead Online Delay Calibration. - Sivasubramaniam Krishnamurthy; Somnath Paul; Swarup Bhunia (ISQED, 2007)

VIm-Scan: A Low Overhead Scan Design Approach for Protection of Secret Key in Scan-Based Secure Chips. - Somnath Paul; Rajat Subhra Chakraborty; Swarup Bhunia (VTS, 2007)

MBARC: A scalable memory based reconfigurable computing framework for nanoscale devices. - Somnath Paul; Swarup Bhunia (ASP-DAC, 2008)

Collective computing based on swarm intelligence. - Seetharam Narasimhan; Somnath Paul; Swarup Bhunia (DAC, 2008)

Reconfigurable computing using content addressable memory for improved performance and resource usage. - Somnath Paul; Swarup Bhunia (DAC, 2008)

Harvesting Wasted Heat in a Microprocessor Using Thermoelectric Generators: Modeling, Analysis and Measurement. - Yu Zhou; Somnath Paul; Swarup Bhunia (DATE, 2008)

On-Demand Transparency for Improving Hardware Trojan Detectability. - Rajat Subhra Chakraborty; Somnath Paul; Swarup Bhunia (HOST, 2008)

Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approaches. - Somnath Paul; Saibal Mukhopadhyay; Swarup Bhunia (ICCAD, 2008)

Towards Uniform Temperature Distribution in SOI Circuits Using Carbon Nanotube Based Thermal Interconnect. - Yu Zhou; Somnath Paul; Swarup Bhunia (ISQED, 2008)

Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits. - Rajat Subhra Chakraborty; Somnath Paul; Swarup Bhunia (VLSI Design, 2008)

MERO: A Statistical Approach for Hardware Trojan Detection. - Rajat Subhra Chakraborty; Francis G. Wolff; Somnath Paul; Christos A. Papachristou; Swarup Bhunia (CHES, 2009)

A circuit-software co-design approach for improving EDP in reconfigurable frameworks. - Somnath Paul; Subho Chatterjee; Saibal Mukhopadhyay; Swarup Bhunia (ICCAD, 2009)

Computing with nanoscale memory: Model and architecture. - Somnath Paul; Swarup Bhunia (NANOARCH, 2009)

Low-power hybrid complementary metaloxide- semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping. - Rajat Subhra Chakraborty; Somnath Paul; Yu Zhou; Swarup Bhunia (IET Comput. Digit. Tech., 2009)

System level self-healing for parametric yield and reliability improvement under power bound. - Seetharam Narasimhan; Somnath Paul; Rajat Subhra Chakraborty; Francis G. Wolff; Christos A. Papachristou; Daniel J. Weyer; Swarup Bhunia (AHS, 2010)

Multiple-Parameter Side-Channel Analysis: A Non-invasive Hardware Trojan Detection Approach. - Seetharam Narasimhan; Rajat Subhra Chakraborty; Dongdong Du; Somnath Paul; Francis G. Wolff; Christos A. Papachristou; Kaushik Roy 001; Swarup Bhunia (HOST, 2010)

VAIL: variation-aware issue logic and performance binning for processor yield and profit improvement. - Somnath Paul; Swarup Bhunia (ISLPED, 2010)

Low-overhead Fmax calibration at multiple operating points using delay-sensitivity-based path selection. - Somnath Paul; Hamid Mahmoodi; Swarup Bhunia (ACM Trans. Design Autom. Electr. Syst., 2010)

Memory based computing: reshaping the fine-grained logic in a reconfigurable framework (abstract only). - Somnath Paul; Swarup Bhunia (FPGA, 2011)

NEMTronics: Symbiotic integration of nanoelectronic and nanomechanical devices for energy-efficient adaptive computing. - Xinmu Wang; Seetharam Narasimhan; Somnath Paul; Swarup Bhunia (NANOARCH, 2011)

Energy-Efficient Reconfigurable Computing Using a Circuit-Architecture-Software Co-Design Approach. - Somnath Paul; Subho Chatterjee; Saibal Mukhopadhyay; Swarup Bhunia (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Reliability-Driven ECC Allocation for Multiple Bit Error Resilience in Processor Cache. - Somnath Paul; Fang Cai; Xinmiao Zhang 001; Swarup Bhunia (IEEE Trans. Computers, 2011)

Dynamic Transfer of Computation to Processor Cache for Yield and Reliability Improvement. - Somnath Paul; Swarup Bhunia (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Energy-Efficient Application Mapping in FPGA through Computation in Embedded Memory Blocks. - Anandaroop Ghosh; Somnath Paul; Swarup Bhunia (VLSI Design, 2012)

Width-Aware Fine-Grained Dynamic Supply Gating: A Design Methodology for Low-Power Datapath and Memory. - Lei Wang; Somnath Paul; Swarup Bhunia (VLSI Design, 2012)

On the Maximal Distance spectral radius in a Class of bicyclic Graphs. - Somnath Paul (Discret. Math. Algorithms Appl., 2012)

Reconfigurable ECC for adaptive protection of memory. - Abhishek Basak; Somnath Paul; Jangwon Park; Jongsun Park 001; Swarup Bhunia (MWSCAS, 2013)

An Improved g m /I D Methodology for Ultra-Low-Power Nano-Scale CMOS OTA Design. - Somnath Paul; Abhijit Dana; Soumya Pandit (VDAT, 2013)

Graph Transformation and Distance spectral radius. - Milan Nath; Somnath Paul (Discret. Math. Algorithms Appl., 2013)

Hardware Trojan Detection by Multiple-Parameter Side-Channel Analysis. - Seetharam Narasimhan; Dongdong Du; Rajat Subhra Chakraborty; Somnath Paul; Francis G. Wolff; Christos A. Papachristou; Kaushik Roy 001; Swarup Bhunia (IEEE Trans. Computers, 2013)

Energy-efficient hardware acceleration through computing in the memory. - Somnath Paul; Robert Karam; Swarup Bhunia; Ruchir Puri (DATE, 2014)

Robust low-power reconfigurable computing with a variation-aware preferential design approach. - Somnath Paul; Saibal Mukhopadhyay; Swarup Bhunia (ICICDT, 2014)

On the Minimal Distance spectral radius in the Class of bicyclic graphs. - Milan Nath; Somnath Paul (Discret. Math. Algorithms Appl., 2014)

A note on the Distance spectral radius of some graphs. - Milan Nath; Somnath Paul (Discret. Math. Algorithms Appl., 2014)

Improving Energy Efficiency in FPGA Through Judicious Mapping of Computation to Embedded Memory Blocks. - Anandaroop Ghosh; Somnath Paul; Jongsun Park 001; Swarup Bhunia (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A Variation-Aware Preferential Design Approach for Memory-Based Reconfigurable Computing. - Somnath Paul; Saibal Mukhopadhyay; Swarup Bhunia (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Exploring Spin Transfer Torque Devices for Unconventional Computing. - Kaushik Roy 001; Deliang Fan; Xuanyao Fong; Yusung Kim 002; Mrigank Sharad; Somnath Paul; Subho Chatterjee; Swarup Bhunia; Saibal Mukhopadhyay (IEEE J. Emerg. Sel. Topics Circuits Syst., 2015)

MAHA: An Energy-Efficient Malleable Hardware Accelerator for Data-Intensive Applications. - Somnath Paul; Aswin Raghav Krishna; Wenchao Qian; Robert Karam; Swarup Bhunia (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Forward table-based presynaptic event-triggered spike-timing-dependent plasticity. - Bruno U. Pedroni; Sadique Sheik; Siddharth Joshi 001; Georgios Detorakis; Somnath Paul; Charles Augustine; Emre Neftci; Gert Cauwenberghs (BioCAS, 2016)

Membrane-dependent neuromorphic learning rule for unsupervised spike pattern detection. - Sadique Sheik; Somnath Paul; Charles Augustine; Gert Cauwenberghs (BioCAS, 2016)

Synaptic sampling in hardware spiking neural networks. - Sadique Sheik; Somnath Paul; Charles Augustine; Chinnikrishna Kothapalli; Muhammad M. Khellah; Gert Cauwenberghs; Emre Neftci (ISCAS, 2016)

An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS. - Somnath Paul; Vinayak Honkote; Ryan Gary Kim; Turbo Majumder; Paolo A. Aseron; Vaughn Grossnickle; Robert Sankman; Debendra Mallik; Sandeep Jain; Sriram R. Vangal; James W. Tschanz; Vivek De (VLSI Circuits, 2016)

Event-driven Random Back-Propagation: Enabling Neuromorphic Deep Learning Machines. - Emre Neftci; Charles Augustine; Somnath Paul; Georgios Detorakis (CoRR, 2016)

On distance and distance Laplacian spectra of corona of two graphs. - Somnath Paul (Discret. Math. Algorithms Appl., 2016)

An Embedded Memory-Centric Reconfigurable Hardware Accelerator for Security Applications. - Christopher Babecki; Wenchao Qian; Somnath Paul; Robert Karam; Swarup Bhunia (IEEE Trans. Computers, 2016)

Event-driven random backpropagation: Enabling neuromorphic deep learning machines. - Emre Neftci; Charles Augustine; Somnath Paul; Georgios Detorakis (ISCAS, 2017)

Neural and Synaptic Array Transceiver: A Brain-Inspired Computing Framework for Embedded Learning. - Georgios Detorakis; Sadique Sheik; Charles Augustine; Somnath Paul; Bruno U. Pedroni; Nikil D. Dutt; Jeffrey L. Krichmar; Gert Cauwenberghs; Emre Neftci (CoRR, 2017)

Adaptive ECC for Tailored Protection of Nanoscale Memory. - Dongyeob Shin; Jongsun Park 001; Jangwon Park; Somnath Paul; Swarup Bhunia (IEEE Des. Test, 2017)

Memory-Centric Reconfigurable Accelerator for Classification and Machine Learning Applications. - Robert Karam; Somnath Paul; Ruchir Puri; Swarup Bhunia (ACM J. Emerg. Technol. Comput. Syst., 2017)

A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications. - Somnath Paul; Vinayak Honkote; Ryan Gary Kim; Turbo Majumder; Paolo A. Aseron; Vaughn Grossnickle; Robert Sankman; Debendra Mallik; Tao Wang; Sriram R. Vangal; James W. Tschanz; Vivek De (IEEE J. Solid State Circuits, 2017)

ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware. - Wenchao Qian; Christopher Babecki; Robert Karam; Somnath Paul; Swarup Bhunia (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Small-footprint Spiking Neural Networks for Power-efficient Keyword Spotting. - Bruno U. Pedroni; Sadique Sheik; Hesham Mostafa; Somnath Paul; Charles Augustine; Gert Cauwenberghs (BioCAS, 2018)

An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. - Pascal Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (ISSCC, 2018)

On the distance signless Laplacian spectral radius and the distance signless Laplacian energy of graphs. - Abdollah Alhevaz; Maryam Baghipur; Somnath Paul (Discret. Math. Algorithms Appl., 2018)

The spectra of a new join of graphs. - Somnath Paul (Discret. Math. Algorithms Appl., 2018)

Conjugate Laplacian matrices of a graph. - Somnath Paul (Discret. Math. Algorithms Appl., 2018)

An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{ text{MIN}}$ Optimization. - Pascal Andreas Meinerzhagen; Carlos Tokunaga; Andres Malavasi; Vaibhav A. Vaidya; Ashwin Mendon; Deepak Mathaikutty; Jaydeep Kulkarni; Charles Augustine; Minki Cho; Stephen T. Kim; George E. Matthew; Rinkle Jain; et al. (IEEE J. Solid State Circuits, 2019)

2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads. - Charles Augustine; Somnath Paul; Turbo Majumder; James W. Tschanz; Muhammad M. Khellah; Vivek De (VLSI Circuits, 2020)

A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. - Somnath Paul; Turbo Majumder; Charles Augustine; Andres F. Malavasi; S. Usirikayala; Raghavan Kumar; Jisna Kollikunnel; S. Chhabra; Satish Yada; M. L. Barajas; Carlos Ornelas; Dan Lake; et al. (VLSI Circuits, 2020)

On the sum of the distance signless Laplacian eigenvalues of a graph and some inequalities involving them. - Abdollah Alhevaz; Maryam Baghipur; Ebrahim Hashemi; Somnath Paul (Discret. Math. Algorithms Appl., 2020)

GenomicsBench: A Benchmark Suite for Genomics. - Arun Subramaniyan 001; Yufeng Gu; Timothy Dunn; Somnath Paul; Md. Vasimuddin; Sanchit Misra; David T. Blaauw; Satish Narayanasamy; Reetuparna Das (ISPASS, 2021)

Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities. - Sriram R. Vangal; Somnath Paul; Steven Hsu; Amit Agarwal 001; Saurabh Kumar 003; Ram Krishnamurthy 001; Harish Krishnamurthy; James W. Tschanz; Vivek De; Chris H. Kim (IEEE Trans. Very Large Scale Integr. Syst., 2021)

GenDP: A Framework of Dynamic Programming Acceleration for Genome Sequencing Analysis. - Yufeng Gu; Arun Subramaniyan 001; Timothy Dunn; Alireza Khadem; Kuan-Yu Chen 001; Somnath Paul; Mohammad Vasimuddin; Sanchit Misra; David T. Blaauw; Satish Narayanasamy; Reetuparna Das (Commun. ACM, 2025)