Resource sharing in pipelined CDFG synthesis. - Somsubhra Mondal; Seda Ogrenci Memik (ASP-DAC, 2005)

Hierarchical LUT structures for leakage power reduction (abstract only). - Somsubhra Mondal; Seda Ogrenci Memik; Debasish Das (FPGA, 2005)

Fine-grain leakage optimization in SRAM based FPGAs. - Somsubhra Mondal; Seda Ogrenci Memik (ACM Great Lakes Symposium on VLSI, 2005)

A low power FPGA routing architecture. - Somsubhra Mondal; Seda Ogrenci Memik (ISCAS (2), 2005)

A Sensor Distribution Algorithm for FPGAs with Minimal Dynamic Reconfiguration Overhead. - Rajarshi Mukherjee; Somsubhra Mondal; Seda Ogrenci Memik (ERSA, 2006)

Pre-synthesis Queue Size Estimation of Streaming Data Flow Graphs. - Somsubhra Mondal; Seda Ogrenci Memik; Nikolaos Bellas (FCCM, 2006)

Power Optimization Techniques for SRAM-Based FPGAs. - Somsubhra Mondal; Seda Ogrenci Memik (FPL, 2006)

Pre-Synthesis Area Estimation of Reconfigurable Streaming Accelerators. - Somsubhra Mondal; Seda Ogrenci Memik; Nikolaos Bellas (FPL, 2006)

Thermal sensor allocation and placement for reconfigurable systems. - Rajarshi Mukherjee; Somsubhra Mondal; Seda Ogrenci Memik (ICCAD, 2006)

Fine-grain thermal profiling and sensor insertion for FPGAs. - Somsubhra Mondal; Rajarshi Mukherjee; Seda Ogrenci Memik (ISCAS, 2006)

Presynthesis Area Estimation of Reconfigurable Streaming Accelerators. - Seda Ogrenci Memik; Nikolaos Bellas; Somsubhra Mondal (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

A high-level clustering algorithm targeting dual Vdd FPGAs. - Rajarshi Mukherjee; Song Liu; Seda Ogrenci Memik; Somsubhra Mondal (ACM Trans. Design Autom. Electr. Syst., 2008)