Characterizing and Exploiting Task-Load Variability and Correlation for Energy Management in multi-core systems. - Soner Yaldiz; Alper Demir 001; Serdar Tasiran; Paolo Ienne; Yusuf Leblebici (ESTIMedia, 2005)

Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study. - Soner Yaldiz; Alper Demir 001; Serdar Tasiran (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

SRAM parametric failure analysis. - Jian Wang 100; Soner Yaldiz; Xin Li 001; Lawrence T. Pileggi (DAC, 2009)

Efficient statistical analysis of read timing failures in SRAM circuits. - Soner Yaldiz; Umut Arslan; Xin Li 001; Larry T. Pileggi (ISQED, 2009)

Indirect phase noise sensing for self-healing voltage controlled oscillators. - Soner Yaldiz; Vehbi Calayir; Xin Li 001; Lawrence T. Pileggi; Arun Natarajan 001; Mark A. Ferriss; José A. Tierno (CICC, 2011)

A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS. - Jean-Olivier Plouchart; Mark A. Ferriss; Arun Natarajan 001; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; Aydin Babakhani; Soner Yaldiz; Lawrence T. Pileggi; Ramesh Harjani; et al. (CICC, 2012)

An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS. - Mark A. Ferriss; Jean-Olivier Plouchart; Arun Natarajan 001; Alexander V. Rylyakov; Benjamin D. Parker; Aydin Babakhani; Soner Yaldiz; Bodhisatwa Sadhu; Alberto Valdes-Garcia; José A. Tierno; Daniel J. Friedman (VLSIC, 2012)

Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion. - Shupeng Sun; Fa Wang; Soner Yaldiz; Xin Li 001; Lawrence T. Pileggi; Arun Natarajan 001; Mark A. Ferriss; Jean-Olivier Plouchart; Bodhisatwa Sadhu; Benjamin D. Parker; Alberto Valdes-Garcia; Mihai A. T. Sanduleanu; et al. (CICC, 2013)

Formal verification of phase-locked loops using reachability analysis and continuization. - Matthias Althoff; Akshay Rajhans; Bruce H. Krogh; Soner Yaldiz; Xin Li 001; Larry T. Pileggi (Commun. ACM, 2013)

An Integral Path Self-Calibration Scheme for a Dual-Loop PLL. - Mark A. Ferriss; Jean-Olivier Plouchart; Arun Natarajan 001; Alexander V. Rylyakov; Benjamin D. Parker; José A. Tierno; Aydin Babakhani; Soner Yaldiz; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Daniel J. Friedman (IEEE J. Solid State Circuits, 2013)

A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. - Bodhisatwa Sadhu; Mark A. Ferriss; Arun Natarajan 001; Soner Yaldiz; Jean-Olivier Plouchart; Alexander V. Rylyakov; Alberto Valdes-Garcia; Benjamin D. Parker; Aydin Babakhani; Scott K. Reynolds; Xin Li 001; Lawrence T. Pileggi; et al. (IEEE J. Solid State Circuits, 2013)

A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. - Jean-Olivier Plouchart; Mark A. Ferriss; Arun Natarajan 001; Alberto Valdes-Garcia; Bodhisatwa Sadhu; Alexander V. Rylyakov; Benjamin D. Parker; Michael P. Beakes; Aydin Babakhani; Soner Yaldiz; Larry T. Pileggi; Ramesh Harjani; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing". - Bodhisatwa Sadhu; Mark A. Ferriss; Arun S. Natarajan 001; Soner Yaldiz; Jean-Olivier Plouchart; Alexander V. Rylyakov; Alberto Valdes-Garcia; Benjamin D. Parker; Aydin Babakhani; Scott K. Reynolds; Xin Li 001; Lawrence T. Pillage; et al. (IEEE J. Solid State Circuits, 2013)

Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits. - Shupeng Sun; Fa Wang; Soner Yaldiz; Xin Li 001; Lawrence T. Pileggi; Arun Natarajan 001; Mark A. Ferriss; Jean-Olivier Plouchart; Bodhisatwa Sadhu; Benjamin D. Parker; Alberto Valdes-Garcia; Mihai A. T. Sanduleanu; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology. - Amr Lotfy; Syed Feruz Syed Farooq; Qi S. Wang; Soner Yaldiz; Praveen Mosalikanti; Nasser A. Kurd (CICC, 2015)

The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk). - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Yishuang Lin; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Soner Yaldiz; et al. (ICCAD, 2020)

Common-Centroid Layouts for Analog Circuits: Advantages and Limitations. - Arvind K. Sharma; Meghna Madhusudan; Steven M. Burns; Parijat Mukherjee; Soner Yaldiz; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2021)

Performance-Aware Common-Centroid Placement and Routing of Transistor Arrays in Analog Circuits. - Arvind K. Sharma; Meghna Madhusudan; Steven M. Burns; Soner Yaldiz; Parijat Mukherjee; Ramesh Harjani; Sachin S. Sapatnekar (ICCAD, 2021)

Machine Learning Techniques in Analog Layout Automation. - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Yishuang Lin; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Steven M. Burns; Ramesh Harjani; Jiang Hu; Parijat Mukherjee; Soner Yaldiz; et al. (ISPD, 2021)

ALIGN: A System for Automating Analog Layout. - Tonmoy Dhar; Kishor Kunal; Yaguang Li; Meghna Madhusudan; Jitesh Poojary; Arvind K. Sharma; Wenbin Xu; Steven M. Burns; Ramesh Harjani; Jiang Hu; Desmond A. Kirkpatrick; Parijat Mukherjee; et al. (IEEE Des. Test, 2021)

A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement. - Tonmoy Dhar; Ramprasath S 001; Jitesh Poojary; Soner Yaldiz; Steven M. Burns; Ramesh Harjani; Sachin S. Sapatnekar (DATE, 2022)

Analog/Mixed-Signal Layout Optimization using Optimal Well Taps. - Ramprasath S 001; Meghna Madhusudan; Arvind K. Sharma; Jitesh Poojary; Soner Yaldiz; Ramesh Harjani; Steven M. Burns; Sachin S. Sapatnekar (ISPD, 2022)

Analog Layout Automation On Advanced Process Technologies. - Soner Yaldiz (ISPD, 2023)

A Generalized Methodology for Well Island Generation and Well-tap Insertion in Analog/Mixed-signal Layouts. - Ramprasath Srinivasa Gopalakrishnan; Meghna Madhusudan; Arvind K. Sharma; Jitesh Poojary; Soner Yaldiz; Ramesh Harjani; Steven M. Burns; Sachin S. Sapatnekar (ACM Trans. Design Autom. Electr. Syst., 2023)

Constructive Place-and-Route for FinFET-Based Transistor Arrays in Analog Circuits Under Nonlinear Gradients. - Arvind K. Sharma; Meghna Madhusudan; Steven M. Burns; Soner Yaldiz; Parijat Mukherjee; Ramesh Harjani; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)