A buffer planning algorithm based on dead space redistribution. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Yici Cai; Chung-Kuan Cheng; Jun Gu (ASP-DAC, 2003)

VLSI module placement with pre-placed modules and considering congestion using solution space smoothing. - Sheqin Dong; Xianlong Hong; Xin Qi; Ruijie Wang 006; Song Chen 001; Jun Gu (ASP-DAC, 2003)

Dynamic global buffer planning optimization based on detail block locating and congestion analysis. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Yici Cai; Chung-Kuan Cheng; Jun Gu (DAC, 2003)

Evaluating a bounded slice-line grid assignment in O(nlogn) time. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Yici Cai; Chung-Kuan Cheng; Jun Gu (ISCAS (4), 2003)

Arbitrary convex and concave rectilinear block packing based on corner block list. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Yici Cai; Song Chen 001; Chung-Kuan Cheng; Jun Gu (ISCAS (5), 2003)

An integrated floorplanning with an efficient buffer planning algorithm. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Yici Cai; Chung-Kuan Cheng; Jun Gu (ISPD, 2003)

VLSI Module Placement with Pre-Placed Modules and with Consideration of Congestion Using Solution Space Smoothing. - Sheqin Dong; Xianlong Hong; Song Chen 001; Xin Qi; Ruijie Wang 006; Jun Gu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003)

A buffer planning algorithm with congestion optimization. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Yici Cai; Chung-Kuan Cheng; Jun Gu (ASP-DAC, 2004)

Buffer allocation algorithm with consideration of routing congestion. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Yici Cai; Chung-Kuan Cheng; Jun Gu (ASP-DAC, 2004)

A buffer planning algorithm for chip-level floorplanning. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Yici Cai; Chung-Kuan Cheng; Jun Gu (Sci. China Ser. F Inf. Sci., 2004)

Fast Evaluation of Bounded Slice-Line Grid. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Chung-Kuan Cheng; Jun Gu (J. Comput. Sci. Technol., 2004)

A New Buffer Planning Algorithm Based on Room Resizing. - Hongjie Bai; Sheqin Dong; Xianlong Hong; Song Chen 001 (EUC, 2005)

VLSI block placement with alignment constraints based on corner block list. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Chung-Kuan Cheng (ISCAS (6), 2005)

Performance constrained floorplanning based on partial clustering [IC layout]. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Chung-Kuan Cheng (ISCAS (2), 2005)

Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning. - Song Chen 001; Xianlong Hong; Sheqin Dong; Yuchun Ma; Chung-Kuan Cheng (ISQED, 2005)

Buffer Planning Algorithm Based on Partial Clustered Floorplanning. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Chung-Kuan Cheng (ISQED, 2005)

Buffer planning as an Integral part of floorplanning with consideration of routing congestion. - Yuchun Ma; Xianlong Hong; Sheqin Dong; Song Chen 001; Chung-Kuan Cheng; Jun Gu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

On the Number of 3-D IC Floorplan Configurations and a Solution Perturbation Method with Good Convergence. - Song Chen 001; Takeshi Yoshimura (APCCAS, 2006)

Buffer planning based on block exchanging. - Hongjie Bai; Sheqin Dong; Xianlong Hong; Song Chen 001 (ISCAS, 2006)

VLSI Block Placement With Alignment Constraints. - Song Chen 001; Sheqin Dong; Xianlong Hong; Yuchun Ma; Chung-Kuan Cheng (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A stable fixed-outline floorplanning method. - Song Chen 001; Takeshi Yoshimura (ISPD, 2007)

Max-Flow Scheduling in High-Level Synthesis. - Liangwei Ge; Song Chen 001; Kazutoshi Wakabayashi; Takashi Takenaka; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

A Synthesis Method of General Floating-Point Arithmetic Units by Aligned Partition. - Liangwei Ge; Song Chen 001; Yuichi Nakamura 002; Takeshi Yoshimura (IPSJ Trans. Syst. LSI Des. Methodol., 2008)

Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs. - Song Chen 001; Takeshi Yoshimura (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Voltage-island driven floorplanning considering level-shifter positions. - Bei Yu 001; Sheqin Dong; Satoshi Goto; Song Chen 001 (ACM Great Lakes Symposium on VLSI, 2009)

A generalized V-shaped multilevel method for large scale floorplanning. - Song Chen 001; Zheng Xu; Takeshi Yoshimura (ISQED, 2009)

Lagrangian Relaxation Based Inter-Layer Signal Via Assignment for 3-D ICs. - Song Chen 001; Liangwei Ge; Mei-Fang Chiang; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Voltage and Level-Shifter Assignment Driven Floorplanning. - Bei Yu 001; Sheqin Dong; Song Chen 001; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Exploration of Schedule Space by Random Walk. - Liangwei Ge; Song Chen 001; Takeshi Yoshimura (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Post-scheduling frequency assignment for energy-efficient high-level synthesis. - Ru Liu; Song Chen 001; Takeshi Yoshimura (APCCAS, 2010)

Floorplanning and topology generation for application-specific network-on-chip. - Bei Yu 001; Sheqin Dong; Song Chen 001; Satoshi Goto (ASP-DAC, 2010)

A revisit to voltage partitioning problem. - Tao Lin; Sheqin Dong; Bei Yu 001; Song Chen 001; Satoshi Goto (ACM Great Lakes Symposium on VLSI, 2010)

Whitespace insertion for through-silicon via planning on 3-D SoCs. - Wei Zhong; Song Chen 001; Takeshi Yoshimura (ISCAS, 2010)

Redundant via Insertion: Removing Design Rule Conflicts and Balancing via Density. - Song Chen 001; Jianwei Shen 003; Wei Guo; Mei-Fang Chiang; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints. - Song Chen 001; Takeshi Yoshimura (Integr., 2010)

Through-Silicon-Via assignment for 3D ICs. - Jianchang Ao; Sheqin Dong; Song Chen 001; Satoshi Goto (ASICON, 2011)

Mobility overlap-removal based timing-constrained scheduling. - Song Chen 001; Yuan Yao; Takeshi Yoshimura (ASICON, 2011)

An effecient level-shifter floorplanning method for Multi-voltage design. - Xiaolin Zhang; Zhi Lin; Song Chen 001; Takeshi Yoshimura (ASICON, 2011)

Network flow-based simultaneous retiming and slack budgeting for low power design. - Bei Yu 001; Sheqin Dong; Yuchun Ma; Tao Lin; Yu Wang 002; Song Chen 001; Satoshi Goto (ASP-DAC, 2011)

Floorplanning driven Network-on-Chip synthesis for 3-D SoCs. - Wei Zhong; Song Chen 001; Fei Ma; Takeshi Yoshimura; Satoshi Goto (ISCAS, 2011)

Novel and efficient min cut based voltage assignment in gate level. - Tao Lin; Sheqin Dong; Song Chen 001; Yuchun Ma; Ou He; Satoshi Goto (ISQED, 2011)

Application-specific Network-on-Chip synthesis: Cluster generation and network component insertion. - Wei Zhong; Bei Yu 001; Song Chen 001; Takeshi Yoshimura; Sheqin Dong; Satoshi Goto (ISQED, 2011)

Linear optimal one-sided single-detour algorithm for untangling twisted bus. - Tao Lin; Sheqin Dong; Song Chen 001; Satoshi Goto (ASP-DAC, 2012)

Practically scalable floorplanning with voltage island generation. - Song Chen 001; Xiaolin Zhang; Takeshi Yoshimura (ISLPED, 2012)

Application-Specific Network-on-Chip synthesis with topology-aware floorplanning. - Bo Huang; Song Chen 001; Wei Zhong; Takeshi Yoshimura (SBCCI, 2012)

Port assignment for interconnect reduction in high-level synthesis. - Cong Hao; Song Chen 001; Takeshi Yoshimura (VLSI-DAT, 2012)

Floorplanning for High Utilization of Heterogeneous FPGAs. - Nan Liu 002; Song Chen 001; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System. - Haiqi Wang; Sheqin Dong; Tao Lin; Song Chen 001; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Cluster Generation and Network Component Insertion for Topology Synthesis of Application-Specific Network-on-Chips. - Wei Zhong; Takeshi Yoshimura; Bei Yu 001; Song Chen 001; Sheqin Dong; Satoshi Goto (IEICE Trans. Electron., 2012)

Interconnection allocation between functional units and registers in High-Level Synthesis. - Cong Hao; Nan Wang 003; Song Chen 001; Takeshi Yoshimura; Min-You Wu (ASICON, 2013)

Power and resource aware scheduling with multiple voltages. - Haoran Zhang; Cong Hao; Nan Wang 003; Song Chen 001; Takeshi Yoshimura (ASICON, 2013)

Lagrangian relaxation based pin assignment and Through-Silicon Via planning for 3-D SoCs. - Wei Zhong; Song Chen 001; Yang Geng; Takeshi Yoshimura (ASICON, 2013)

Network simplex method based Multiple Voltage Scheduling in Power-efficient High-level synthesis. - Cong Hao; Song Chen 001; Takeshi Yoshimura (ASP-DAC, 2013)

Topology-aware floorplanning for 3D application-specific Network-on-Chip synthesis. - Bo Huang; Song Chen 001; Wei Zhong; Takeshi Yoshimura (ISCAS, 2013)

Mobility overlap-removal based leakage power aware scheduling in high-level synthesis. - Nan Wang 003; Song Chen 001; Yuhuan Sun; Takeshi Yoshimura (ISCAS, 2013)

Delay-driven layer assignment in global routing under multi-tier interconnect structure. - Jianchang Ao; Sheqin Dong; Song Chen 001; Satoshi Goto (ISPD, 2013)

Min-cut based leakage power aware scheduling in high-level synthesis. - Nan Wang 003; Song Chen 001; Takeshi Yoshimura (ISQED, 2013)

Resource-Aware Multi-Layer Floorplanning for Partially Reconfigurable FPGAs. - Nan Liu 002; Song Chen 001; Takeshi Yoshimura (IEICE Trans. Electron., 2013)

Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips. - Wei Zhong; Song Chen 001; Bo Huang; Takeshi Yoshimura; Satoshi Goto (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Leakage Power Aware Scheduling in High-Level Synthesis. - Nan Wang 003; Song Chen 001; Cong Hao; Haoran Zhang; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Mobility Overlap-Removal-Based Leakage Power and Register-Aware Scheduling in High-Level Synthesis. - Nan Wang 003; Song Chen 001; Wei Zhong; Nan Liu 002; Takeshi Yoshimura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014)

Lagrangian relaxation based topology synthesis for Application-Specific Network-on-Chips. - Jinglei Huang; Zhigang Li; Wei Zhong; Song Chen 001 (ASICON, 2015)

A full layer parallel QC-LDPC decoder for WiMAX and Wi-Fi. - Wenchao Zhang; Song Chen 001; Xuefei Bai; Dajiang Zhou (ASICON, 2015)

Irregularly shaped voltage islands generation with hazard and heal strategy. - Zhen Meng; Song Chen 001; Lu Huang (ISQED, 2015)

Real-Time Hardware Stereo Matching Using Guided Image Filter. - Chen Yang; Yan Li 068; Wei Zhong; Song Chen 001 (ACM Great Lakes Symposium on VLSI, 2016)

Combining the ant system algorithm and simulated annealing for 3D/2D fixed-outline floorplanning. - Qi Xu; Song Chen 001; Bin Li 025 (Appl. Soft Comput., 2016)

Floorplanning and Topology Synthesis for Application-Specific Network-on-Chips with RF-Interconnect. - Jinglei Huang; Song Chen 001; Wei Zhong; Wenchao Zhang; Shengxi Diao; Fujiang Lin (ACM Trans. Design Autom. Electr. Syst., 2016)

Leakage-Power-Aware Scheduling With Dual-Threshold Voltage Design. - Nan Wang 003; Wei Zhong; Cong Hao; Song Chen 001; Takeshi Yoshimura; Yu Zhu 005 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Integer linear programming based fault-tolerant topology synthesis for application-specific NoC. - Zhigang Li; Jinglei Huang; Qi Xu; Song Chen 001 (ASICON, 2017)

A fully pipelined hardware architecture for convolutional neural network with low memory usage and DRAM bandwidth. - Zhiwei Li 006; Yan Li 068; Song Chen 001; Feng Wu 001 (ASICON, 2017)

Memristor-based material implication logic design for full adders. - Mengting Li; Wenhao Sun; Zhimin Lu; Song Chen 001; Feng Wu 001 (ASICON, 2017)

An Integrated Optimization Framework for Partitioning, Scheduling and Floorplanning on Partially Dynamically Reconfigurable FPGAs. - Xiaodong Xu; Qi Xu; Jinglei Huang; Song Chen 001 (ACM Great Lakes Symposium on VLSI, 2017)

Reconfigurable topology synthesis for application-specific noc on partially dynamically reconfigurable FPGAs. - Jinglei Huang; Xiaodong Xu; Lan Yao; Song Chen 001 (SLIP, 2017)

AutoNFT: Architecture synthesis for hardware DFT of length-of-coprime-number products. - Gan Feng; Lan Yao; Song Chen 001 (Integr., 2017)

Fast thermal analysis for fixed-outline 3D floorplanning. - Qi Xu; Song Chen 001 (Integr., 2017)

Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits. - Qi Xu; Song Chen 001; Xiaodong Xu; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC. - Qi Xu; Song Chen 001; Bei Yu 001; Feng Wu 001 (ACM Great Lakes Symposium on VLSI, 2018)

Security-Driven Task Scheduling for Multiprocessor System-on-Chips with Performance Constraints. - Nan Wang 003; Manting Yao; Dongxu Jiang; Song Chen 001; Yu Zhu 005 (ISVLSI, 2018)

Security-Aware Task Scheduling Using Untrusted Components in High-Level Synthesis. - Nan Wang 003; Song Chen 001; Jianmo Ni; Xiaofeng Ling; Yu Zhu 005 (IEEE Access, 2018)

Integrated Optimization of Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems. - Song Chen 001; Jinglei Huang; Xiaodong Xu; Qi Xu (CoRR, 2018)

Lagrangian relaxation-based routing path allocation for application-specific network-on-chips. - Jinglei Huang; Wei Zhong; Zhigang Li; Song Chen 001 (Integr., 2018)

Power-gating-aware scheduling with effective hardware resources optimization. - Nan Wang 003; Wei Zhong; Song Chen 001; Zhiyuan Ma 001; Xiaofeng Ling; Yu Zhu 005 (Integr., 2018)

An Energy-Efficient Systolic Pipeline Architecture for Binary Convolutional Neural Network. - Baicheng Liu; Song Chen 001; Yi Kang; Feng Wu 001 (ASICON, 2019)

Customizing CMOS/ReRAM Hybrid Hardware Architecture for Spiking CNN. - Tianzhi Xue; Baicheng Liu; Wenhao Sun; Song Chen 001; Yi Kang; Feng Wu 001 (ASICON, 2019)

Low-Resource Hardware Architecture for Semi-Global Stereo Matching. - Jue Wang; Zhiwei Li 006; Lan Yao; Song Chen 001; Feng Wu 001 (ISCAS, 2019)

Reconfigurable topology synthesis for application-specific NoC on partially dynamically reconfigurable systems. - Jinglei Huang; Xiaodong Xu; Nan Wang 003; Song Chen 001 (Integr., 2019)

High throughput hardware architecture for accurate semi-global matching. - Yan Li 068; Zhiwei Li 006; Chen Yang; Wei Zhong; Song Chen 001 (Integr., 2019)

Integrating operation scheduling and binding for functional unit power-gating in high-level synthesis. - Nan Wang 003; Song Chen 001; Zhiyuan Ma 001; Xiaofeng Ling; Yu Zhu 005 (Integr., 2019)

Adaptive 3D-IC TSV Fault Tolerance Structure Generation. - Song Chen 001; Qi Xu; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Fault-Tolerant-Driven Clustering for Large Scale Neuromorphic Computing Systems. - Yuting Wu; Bo Ding; Qi Xu; Song Chen 001 (AICAS, 2020)

Synthesizing A Generalized Brain-inspired Interconnection Network for Large-scale Network-on-chip Systems. - Mengke Ge; Qi Xu; Huajie Ruan; Xiaobing Ni; Song Chen 001; Yi Kang (ACM Great Lakes Symposium on VLSI, 2020)

SaD-SLAM: A Visual SLAM Based on Semantic and Depth Information. - Xun Yuan 001; Song Chen 001 (IROS, 2020)

Reliability-Driven Neural Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems. - Junpeng Wang 002; Qi Xu; Bo Yuan 006; Song Chen 001; Bei Yu 001; Feng Wu 001 (ISCAS, 2020)

Realtime CNN-based Keypoint Detector with Sobel Filter and CNN-based Descriptor Trained with Keypoint Candidates. - Xun Yuan 001; Ke Hu; Song Chen 001 (CoRR, 2020)

Fault tolerance in memristive crossbar-based neuromorphic computing systems. - Qi Xu; Song Chen 001; Hao Geng; Bo Yuan 006; Bei Yu 001; Feng Wu 001; Zhengfeng Huang (Integr., 2020)

Generalized Fault-Tolerance Topology Generation for Application-Specific Network-on-Chips. - Song Chen 001; Mengke Ge; Zhigang Li; Jinglei Huang; Qi Xu; Feng Wu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Integrated Optimization of Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems. - Song Chen 001; Jinglei Huang; Xiaodong Xu; Bo Ding; Qi Xu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Memristive Crossbar Mapping for Neuromorphic Computing Systems on 3D IC. - Qi Xu; Hao Geng; Song Chen 001; Bei Yu 001; Feng Wu 001 (ACM Trans. Design Autom. Electr. Syst., 2020)

A Low Power Branch Prediction for Deep Learning on RISC-V Processor. - Mingjian Sun; Yuan Li 059; Song Chen 001; Yi Kang (ASAP, 2021)

Effects of using Multi Voltage Threshold Transistors in Asynchronous Circuits. - Shahzad Haider; Song Chen 001 (ASICON, 2021)

Reliability-Driven Neuromorphic Computing Systems Design. - Qi Xu; Junpeng Wang 002; Hao Geng; Song Chen 001; Xiaoqing Wen (DATE, 2021)

A Low-latency NoC Router Priority Scheme for BFS algorithm. - Lei Ding; Haitao Du; Song Chen 001; Yi Kang (ICTA, 2021)

A Non-volatile Computing-in-Memory ReRAM Macro using Two-bit Current-Mode Sensing Amplifier. - Qiqiao Wu; Wenhao Sun; Junpeng Wang 002; Xuefei Bai; Feng Zhang; Song Chen 001; Yi Kang (NVMSA, 2021)

DRGS: Low-Precision Full Quantization of Deep Neural Network with Dynamic Rounding and Gradient Scaling for Object Detection. - Qiaojun Wu; Yuan Li 059; Song Chen 001; Yi Kang (DMBD (1), 2022)

Real-time CNN-based keypoint detector with Sobel filter and descriptor trained with keypoint candidates. - Ke Hu; Xun Yuan 001; Song Chen 001 (ICMV, 2022)

SAUST: A Scheme for Acceleration of Unstructured Sparse Transformer. - Yifan Song; Shunpeng Zhao; Song Chen 001; Yi Kang (ICTA, 2022)

PCFBCD: An Innovative Approach to Accelerating Collaborative Filtering. - Bin Zhang; Haitao Du; Song Chen 001; Yi Kang (ISCAS, 2022)

Multi-scale Lightweight Neural Network for Real-Time Object Detection. - Yuan Li 059; Qiaojun Wu; Song Chen 001; Yi Kang (PRICAI (3), 2022)

Sense: Model Hardware Co-design for Accelerating Sparse Neural Networks. - Wenhao Sun; Deng Liu; Zhiwei Zou; Wendi Sun; Junpeng Wang 002; Yi Kang; Song Chen 001 (CoRR, 2022)

Task modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems Based on Modern Heterogeneous FPGAs. - Bo Ding; Jinglei Huang; Junpeng Wang 002; Qi Xu; Song Chen 001; Yi Kang (CoRR, 2022)

Real-time infrared small target detection network and accelerator design. - Ke Hu; Wenhao Sun; Zhongbo Nie; Ran Cheng; Song Chen 001; Yi Kang (Integr., 2022)

GoodFloorplan: Graph Convolutional Network and Reinforcement Learning-Based Floorplanning. - Qi Xu; Hao Geng; Song Chen 001; Bo Yuan 006; Cheng Zhuo; Yi Kang; Xiaoqing Wen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Fortune: A New Fault-Tolerance TSV Configuration in Router-Based Redundancy Structure. - Qi Xu; Hao Geng; Tianming Ni; Song Chen 001; Bei Yu 001; Yi Kang; Xiaoqing Wen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Cellular Structure-Based Fault-Tolerance TSV Configuration in 3D-IC. - Qi Xu; Wenhao Sun; Song Chen 001; Yi Kang; Xiaoqing Wen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Generating Brain-Network-Inspired Topologies for Large-Scale NoCs on Monolithic 3D ICs. - Mengke Ge; Xiaobing Ni; Song Chen 001; Yi Kang (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A Resource-Efficient Pipelined Architecture for Real-Time Semi-Global Stereo Matching. - Zhimin Lu; Jue Wang; Zhiwei Li 006; Song Chen 001; Feng Wu 001 (IEEE Trans. Circuits Syst. Video Technol., 2022)

Synthesizing Brain-network-inspired Interconnections for Large-scale Network-on-chips. - Mengke Ge; Xiaobing Ni; Qi Xu; Song Chen 001; Jinglei Huang; Yi Kang; Feng Wu 001 (ACM Trans. Design Autom. Electr. Syst., 2022)

An 1.38nJ/Inference Clock-Free Mixed-Signal Neuromorphic Architecture Using ReL-PSP Function and Computing-in-Memory. - Wenbing Fang; Zihao Xuan; Song Chen 001; Yi Kang (BioCAS, 2023)

GGPA: A General Graph Processing Architecture with Flexible Execution Paradigm. - Bin Zhang; Haitao Du; Song Chen 001; Yi Kang (CF, 2023)

Restructure-Tolerant Timing Prediction via Multimodal Fusion. - Ziyi Wang 010; Siting Liu 002; Yuan Pu 001; Song Chen 001; Tsung-Yi Ho; Bei Yu 001 (DAC, 2023)

A Lightweight Stereo Matching Neural Network Based on Depthwise Separable Convolution. - Zetao Guo; Junpeng Wang 002; Song Chen 001; Yi Kang (ICTA, 2023)

Granular Transistor-Level Approaches for QDI Asynchronous Crossbar Switches. - Shahzad Haider; Song Chen 001 (MWSCAS, 2023)

Efficient Transistor-Level QDI Asynchronous Switch for Neuromorphic Systems. - Shahzad Haider; Junhao Liang; Song Chen 001 (NEWCAS, 2023)

Fine-Grained Transistor-Level QDI Asynchronous Crossbar Switch. - Shahzad Haider; Ke Hu; Song Chen 001 (SOCC, 2023)

Bit-balance: Model-Hardware Co-design for Accelerating NNs by Exploiting Bit-level Sparsity. - Wenhao Sun; Zhiwei Zou; Deng Liu; Wendi Sun; Song Chen 001; Yi Kang (CoRR, 2023)

NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators with 3D-Stacked-DRAM. - Junpeng Wang 002; Mengke Ge; Bo Ding; Qi Xu; Song Chen 001; Yi Kang (CoRR, 2023)

BandMap: Application Mapping with Bandwidth Allocation forCoarse-Grained Reconfigurable Array. - Xiaobing Ni; Jiaheng Ruan; Mengke Ge; Wendi Sun; Song Chen 001; Yi Kang (CoRR, 2023)

AiDAC: A Low-Cost In-Memory Computing Architecture with All-Analog Multi-Bit Compute and Interconnect. - Zihao Xuan; Song Chen 001; Yi Kang (CoRR, 2023)

IOPS: An Unified SpMM Accelerator Based on Inner-Outer-Hybrid Product. - Wenhao Sun; Wendi Sun; Song Chen 001; Yi Kang (CoRR, 2023)

Reliability-Driven Memristive Crossbar Design in Neuromorphic Computing Systems. - Qi Xu; Junpeng Wang 002; Bo Yuan 006; Qi Sun 002; Song Chen 001; Bei Yu 001; Yi Kang; Feng Wu 001 (IEEE Trans Autom. Sci. Eng., 2023)

DDAM: Data Distribution-Aware Mapping of CNNs on Processing-In-Memory Systems. - Junpeng Wang 002; Haitao Du; Bo Ding; Qi Xu; Song Chen 001; Yi Kang (ACM Trans. Design Autom. Electr. Syst., 2023)

Memory-aware Partitioning, Scheduling, and Floorplanning for Partially Dynamically Reconfigurable Systems. - Bo Ding; Jinglei Huang; Qi Xu; Junpeng Wang 002; Song Chen 001; Yi Kang (ACM Trans. Design Autom. Electr. Syst., 2023)

Sense: Model-Hardware Codesign for Accelerating Sparse CNNs on Systolic Arrays. - Wenhao Sun; Deng Liu; Zhiwei Zou; Wendi Sun; Song Chen 001; Yi Kang (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Resist: Robust Network Training for Memristive Crossbar-Based Neuromorphic Computing Systems. - Yongtian Bi; Qi Xu; Hao Geng; Song Chen 001; Yi Kang (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

BusMap: Application Mapping With Bus Routing for Coarse-Grained Reconfigurable Array. - Xiaobing Ni; Mengke Ge; Yongjin Tao; Wendi Sun; Feixiang Duan; Xuefei Bai; Qi Xu; Song Chen 001; Yi Kang (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Task Modules Partitioning, Scheduling and Floorplanning for Partially Dynamically Reconfigurable Systems with Heterogeneous Resources. - Bo Ding; Jinglei Huang; Junpeng Wang 002; Qi Xu; Song Chen 001; Yi Kang (ACM Trans. Design Autom. Electr. Syst., 2023)

DALDet: Depth-Aware Learning Based Object Detection for Autonomous Driving. - Ke Hu; Tongbo Cao; Yuan Li 059; Song Chen 001; Yi Kang (AAAI, 2024)

SPVT: Spiked Pyramid Vision Transformer. - Yazhuo Guo; Yuhan Qin; Song Chen 001; Yi Kang (AICAS, 2024)

ILP-based Multi-Branch CNNs Mapping on Processing-in-Memory Architecture. - Haodong Han; Junpeng Wang 002; Bo Ding; Song Chen 001 (AICAS, 2024)

Parallel Multi-Objective Bayesian Optimization Framework for CGRA Microarchitecture. - Bing Li; Wendi Sun; Xiaobing Ni; Kaixuan He; Qi Xu; Song Chen 001; Yi Kang (DATE, 2024)

Miracle: Multi-Action Reinforcement Learning-Based Chip Floorplanning Reasoner. - Bo Yang; Qi Xu; Hao Geng; Song Chen 001; Yi Kang (DATE, 2024)

Communication Minimized Model-Architecture Co-design for Efficient Convolution Acceleration. - Wendi Sun; Wenhao Sun; Yifan Wang; Yi Kang; Song Chen 001 (ACM Great Lakes Symposium on VLSI, 2024)

Efficient Object Detection via Fine-Grained Regularization with Global Initialization. - Binhan Chen; Qiaojun Wu; Song Chen 001; Yi Kang (ICPR (3), 2024)

DP-FFN: Block-Based Dynamic Pooling for Accelerating Feed-Forward Layers in Transformers. - Jie Tang; Shuai Wang; Song Chen 001; Yi Kang (ISCAS, 2024)

SparseMap: Loop Mapping for Sparse CNNs on Streaming Coarse-grained Reconfigurable Array. - Xiaobing Ni; Mengke Ge; Jiaheng Ruan; Song Chen 001; Yi Kang (CoRR, 2024)

Load Balanced PIM-Based Graph Processing. - Xiang Zhao; Song Chen 001; Yi Kang (ACM Trans. Design Autom. Electr. Syst., 2024)

Bit-Balance: Model-Hardware Codesign for Accelerating NNs by Exploiting Bit-Level Sparsity. - Wenhao Sun; Zhiwei Zou; Deng Liu; Wendi Sun; Song Chen 001; Yi Kang (IEEE Trans. Computers, 2024)

AD2VNCS: Adversarial Defense and Device Variation-tolerance in Memristive Crossbar-based Neuromorphic Computing Systems. - Yongtian Bi; Qi Xu; Hao Geng; Song Chen 001; Yi Kang (ACM Trans. Design Autom. Electr. Syst., 2024)

NicePIM: Design Space Exploration for Processing-In-Memory DNN Accelerators With 3-D Stacked-DRAM. - Junpeng Wang 002; Mengke Ge; Bo Ding; Qi Xu; Song Chen 001; Yi Kang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Floorplanning with Edge-aware Graph Attention Network and Hindsight Experience Replay. - Bo Yang; Qi Xu; Hao Geng; Song Chen 001; Bei Yu 001; Yi Kang (ACM Trans. Design Autom. Electr. Syst., 2024)

FASA-DRAM: Reducing DRAM Latency with Destructive Activation and Delayed Restoration. - Haitao Du; Yuhan Qin; Song Chen 001; Yi Kang (ACM Trans. Archit. Code Optim., 2024)

Graph Attention-Based Symmetry Constraint Extraction for Analog Circuits. - Qi Xu; Lijie Wang; Jing Wang 131; Lin Cheng 001; Song Chen 001; Yi Kang (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

ThePlace: Thermal-Aware Placement With Operator Learning-Based Ultra-Fast Simulator. - Xinfei Liu; Siting Liu 002; Bei Yu 001; Song Chen 001; Qi Xu (ASP-DAC, 2025)

Machine Learning-Based Real-Time Detection of Power Analysis Attacks Using Supply Voltage Comparisons. - Nan Wang 003; Ruichao Liu; Yufeng Shan; Yu Zhu 005; Song Chen 001 (ASP-DAC, 2025)

AIPlace: Analog IC Placement with Multi-Task Learning Framework. - Lijie Wang; Jing Wang 131; Song Chen 001; Qi Xu (ASP-DAC, 2025)

Fast shallow multi-subnet detector for real-time object detection. - Yuan Li 059; Mengdie Song; Ke Hu; Song Chen 001; Yi Kang (Eng. Appl. Artif. Intell., 2025)

A neuromorphic hardware architecture based on TTFS coding with temporal quantization for spiking neural networks. - Yuxuan Yang; Qihu Xie; Zihao Xuan; Song Chen 001; Yi Kang (Integr., 2025)

CR-DRAM: Improving DRAM Refresh Energy Efficiency With Inter-Subarray Charge Recycling. - Haitao Du; Hairui Zhu; Song Chen 001; Yi Kang (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Allspark: Workload Orchestration for Visual Transformers on Processing In-Memory Systems. - Mengke Ge; Junpeng Wang 002; Binhan Chen; Yingjian Zhong; Haitao Du; Song Chen 001; Yi Kang (IEEE Trans. Computers, 2025)

HNM-CIM: An Algorithm-Hardware Co-designed SRAM-based CIM for Transformer Acceleration Exploiting Hybrid N:M Sparsity. - Yuang Ma; Yulong Meng; Zihao Xuan; Song Chen 001; Yi Kang (ACM Trans. Design Autom. Electr. Syst., 2025)

IOPS: A Unified SpMM Accelerator Based on Inner-Outer-Hybrid Product. - Wenhao Sun; Wendi Sun; Song Chen 001; Yi Kang (IEEE Trans. Computers, 2025)

EI²Det: Edge-Guided Illumination-Aware Interactive Learning for Visible-Infrared Object Detection. - Ke Hu; Yudong He; Yuan Li 059; Jiayu Zhao; Song Chen 001; Yi Kang (IEEE Trans. Circuits Syst. Video Technol., 2025)

A 3D Unified Analysis Method (3D-UAM) for Wafer-on-Wafer Stacked Near-Memory Structure. - Song Wang; Yixin Guo; Wei Tao; Xuerong Jia; Fujun Bai; Jie Tan; Yubing Wang; Liang Bai; Fuzhi Guo; Qi Liu; Jin Li; Peng Yin; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2025)