Design Retargetable Platform System for Microprocessor Functional Test. - Ling Liu; Wennan Feng; Song Jia; Anping Jiang; Lijiu Ji (Asian Test Symposium, 2003)

Study on the Rainfall Interpolation Algorithm of Distributed Hydrological Model Based on RS. - Xiaoxia Yang; Yong Liang; Song Jia (CCTA (2), 2010)

The Application of Three-Dimensional Visualization Technology in Village Information Service Platform. - Xiaoxia Yang; Yong Liang; Song Jia (CCTA (3), 2010)

Low swing drivers based on charge redistribution. - Fengfeng Wu; Song Jia; Yuan Wang 001; Ganggang Zhang (Sci. China Inf. Sci., 2010)

A novel multi-finger layout strategy for GGnMOS ESD protection device. - Peng Zhang; Yuan Wang 001; Song Jia; Xing Zhang 002 (ASICON, 2011)

Novel single-loop multi-bit sigma-delta modulator using OTA sharing technique without DEM. - Hongyi Li; Yuan Wang 001; Song Jia; Xing Zhang 002 (IEICE Electron. Express, 2011)

Design of novel, semi-transparent flip-flops (STFF) for high speed and low power application. - Xiayu Li; Song Jia; Limin Liu; Yuan Wang 001; Ganggang Zhang (Sci. China Inf. Sci., 2012)

A Pulse-Generator-Free Hybrid Latch Based Flip-Flop (PHLFF). - Xiayu Li; Song Jia; Limin Liu; Yuan Wang 001 (IEICE Trans. Electron., 2012)

A novel dynamic element match technique in current-steering DAC. - Baoguang Liu; Yuan Wang 001; Guangliang Guo; Song Jia; Xing Zhang 002 (ASICON, 2013)

Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits. - Guangyi Lu; Yuan Wang 001; Jian Cao 002; Song Jia; Ganggang Zhang; Xing Zhang 002 (ASICON, 2013)

A current mode sense amplifier with self-compensation circuit for SRAM application. - Heqing Xu; Song Jia; Jiyu Chen; Yuan Wang 001; Gang Du (ASICON, 2013)

Data Convertors Design for Optimization of the DDPL Family. - Song Jia; Li Liu; Xiayu Li; Fengfeng Wu; Yuan Wang 001; Ganggang Zhang (IEICE Trans. Electron., 2013)

A Current-Mirror Winner-Take-All Sense Amplifier for Low Voltage SRAMs. - Song Jia; Heqing Xu; Fengfeng Wu; Yuan Wang 001 (IEICE Trans. Electron., 2013)

Improved CRC Calculation Strategies for 64-bit Serial RapidIO. - Fengfeng Wu; Song Jia; Qinglong Meng; Shigong Lv; Yuan Wang 001; Dacheng Zhang (IEICE Trans. Electron., 2013)

A 10b, 0.7ps resolution coarse-fine time-to-digital converter in 65nm CMOS using a time residue amplifier. - Jiyu Chen; Song Jia; Yuan Wang 001 (ASICON, 2015)

Design on multi-bit adder using sense amplifier-based pass transistor logic for near-threshold voltage operation. - Fangyuan Dang; Yuan Wang 001; Yuequan Liu; Song Jia; Xing Zhang 002 (ASICON, 2015)

A low power and high speed CAM design using pulsed voltage for search-line. - Song Jia; Weiting Li; Wenyi Tang; Yuan Wang 001 (ASICON, 2015)

A reference-less all-digital burst-mode CDR with embedded TDC. - Mengyin Jiang; Yuan Wang 001; Baoguang Liu; Yuequan Liu; Song Jia; Xing Zhang 002 (ASICON, 2015)

A low-power high-speed 32/33 prescaler based on novel divide-by-4/5 unit with improved true single-phase clock logic. - Song Jia; Shilin Yan; Yuan Wang 001; Ganggang Zhang (ISCAS, 2015)

180.5Mbps-8Gbps DLL-based clock and data recovery circuit with low jitter performance. - Yuequan Liu; Yuan Wang 001; Song Jia; Xing Zhang 002 (ISCAS, 2015)

Investigation on the layout strategy of ggNMOS ESD protection devices for uniform conduction behavior and optimal width scaling. - Guangyi Lu; Yuan Wang 001; Lizhong Zhang; Jian Cao 002; Song Jia; Xing Zhang 002 (Sci. China Inf. Sci., 2015)

Simplified carry save adder-based array multiplier scheme and circuits design. - Song Jia; Shigong Lyu; Xiayu Li; Li Liu; Yandong He (Int. J. Circuit Theory Appl., 2015)

A novel low-power and high-speed dual-modulus prescaler based on extended true single-phase clock logic. - Song Jia; Ziyi Wang; Zijin Li; Yuan Wang 001 (ISCAS, 2016)

A novel low-leakage power-rail ESD clamp circuit with adjustable triggering voltage and superior false-triggering immunity for nanoscale applications. - Guangyi Lu; Yuan Wang 001; Jian Cao 002; Song Jia; Xing Zhang 002 (ISCAS, 2016)

Delay-locked loop based frequency quadrupler with wide operating range and fast locking characteristics. - Yuan Wang 001; Yuequan Liu; Mengyin Jiang; Song Jia; Xing Zhang 002 (ISCAS, 2016)

Area-efficient transient power-rail electrostatic discharge clamp circuit with mis-triggering immunity in a 65-nm CMOS process. - Yuan Wang 001; Guangyi Lu; Haibing Guo; Jian Cao 002; Song Jia; Xing Zhang 002 (Sci. China Inf. Sci., 2016)

A Short-Time Three-Phase Single-Rail Precharge Logic against Differential Power Analysis. - Wenyi Tang; Song Jia; Yuan Wang 001 (IEICE Trans. Electron., 2016)

A true single-phase clock dual-modulus prescaler with enhanced robustness against leakage currents. - Song Jia; Ziyi Wang; Shilin Yan; Yuan Wang 001 (Int. J. Circuit Theory Appl., 2016)

A 4.8-6.8 GHz low phase noise LC VCO in 0.13-µm CMOS technology. - Yuan Wang 001; Shanliang Gan; Song Jia; Xing Zhang 002 (Int. J. Circuit Theory Appl., 2016)

Design of a novel ternary SRAM sense amplifier using CNFET. - Zizhao Liu; Tao Pan; Song Jia; Uan Wang (ASICON, 2017)

A reliable true random number generator based on novel chaotic ring oscillator. - Yunfan Yang; Song Jia; Yuan Wang 001; Shaonan Zhang; Chao Liu (ISCAS, 2017)

Delay-locked loop based clock and data recovery with wide operating range and low jitter in a 65-nm CMOS process. - Yuan Wang 001; Yuequan Liu; Song Jia; Xing Zhang 002 (Int. J. Circuit Theory Appl., 2017)

A 1-Gbps reference-less burst-mode CDR with embedded TDC in a 65-nm CMOS process. - Yuan Wang 001; Mengyin Jiang; Baoguang Liu; Song Jia; Xing Zhang 002 (Int. J. Circuit Theory Appl., 2018)

A Novel High-speed FPGA-based True Random Number Generator Based on Chaotic Ring Oscillator. - Xinning Liu; Song Jia; Hanzun Zhang (ASICON, 2019)

Design of an Adaptive Loop Gain Controller Based on Auto-correlation Detection Scheme in All-Digital Phase-Locked Loop. - Sheng Zhang; Song Jia; Hanzun Zhang; Rongshan Wei; Weixin Gai (ASICON, 2019)

An algorithm for calculating coverage rate of WSNs based on geometry decomposition approach. - Xu Hui; Bailing Wang; Song Jia; Haohan Hong; Xiaolei Zhang (Peer-to-Peer Netw. Appl., 2019)

A Prediction Method for Soil Moisture Time Series. - Xiaoxia Yang; Song Jia; Chengming Zhang (ML4CS (3), 2020)

Diversity-aware Web APIs Assignment and Recommendation for Mashup Creation with Compatibility Guarantee. - Wenwen Gong; Huiping Wu; Xiaokang Wang; Xuyun Zhang; Yifei Chen 003; Song Jia; Mohammad Reza Khosravi (CoRR, 2021)

Research on Intelligent Alarm Garbage Processing System Based on Internet of Things. - Xiaotong Zhao; Song Jia; Xiaoxia Yang; Chengming Zhang; Hui Wang (AIoTC, 2022)

A 2.29pJ/b 112Gb/s Wireline Transceiver with RX 4-Tap FFE for Medium-Reach Applications in 28nm CMOS. - Bingyi Ye; Kai Sheng; Weixin Gai; Haowei Niu; Boyang Zhang; Yandong He; Song Jia; Congcong Chen; Jiaqi Yu (ISSCC, 2022)

LEO Enhanced Global Navigation Satellite System (LeGNSS): progress, opportunities, and challenges. - Haibo Ge; Bofeng Li; Song Jia; Liangwei Nie; Tianhao Wu; Zhe Yang; Jingzhe Shang; Yanning Zheng; Maorong Ge (Geo spatial Inf. Sci., 2022)

A 2.29-pJ/b 112-Gb/s Wireline Transceiver With RX Four-Tap FFE for Medium-Reach Applications in 28-nm CMOS. - Bingyi Ye; Kai Sheng; Weixin Gai; Haowei Niu; Boyang Zhang; Yandong He; Song Jia; Congcong Chen; Jiaqi Yu (IEEE J. Solid State Circuits, 2023)

A label noise filtering and label missing supplement framework based on game theory. - Yuwen Liu 003; Rongju Yao; Song Jia; Fan Wang 020; Ruili Wang; Rui Ma 020; Lianyong Qi (Digit. Commun. Networks, 2023)

Study and Analysis of the Thunder Source Location Error Based on Acoustic Ray-Tracing. - Jinyuan Guo; Caixia Wang; Jia Xu; Song Jia; Hui Yang; Zhuling Sun; Xiaobao Wang (Remote. Sens., 2024)

An eDRAM-Based Computing-in-Memory Macro With Full-Valid-Storage and Channel-Wise-Parallelism for Depthwise Neural Network. - Xin Qiao; Youming Yang 002; Chang Xue; Yandong He; Xiaoxin Cui; Song Jia; Yuan Wang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

NeuroREC: A 28-nm Efficient Neuromorphic Processor for Radar Emitter Classification. - Zilin Wang 001; Zehong Ou; Yi Zhong; Youming Yang 002; Li Lun; Hufei Li; Jian Cao 002; Xiaoxin Cui; Song Jia; Yuan Wang 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

Marmotini: A Weight Density Adaptation Architecture With Hybrid Compression Method for Spiking Neural Network. - Zilin Wang 001; Yi Zhong; Zehong Ou; Youming Yang 002; Shuo Feng; Guang Chen; Xiaoxin Cui; Song Jia; Yuan Wang 001 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

CROSSCUT: A Multi-Core Neuromorphic Accelerator Improving Resource-Utilization. - Youming Yang 002; Yi Zhong; Zilin Wang 001; Tao Zhang 140; Li Lun; Yingying Cui; Xiaoxin Cui; Song Jia; Yuan Wang 001 (ISCAS, 2025)

Enabling Fault Isolation in Fault Injection for Automotive-grade Circuits Simulation. - Yulong Liu; Junhao Lin; Yuheng Li; Pingsheng Zhang; Zenan Yan; Yuan Wang 001; Song Jia (ISCAS, 2025)

PAICORE: A 1.9-Million-Neuron 5.181-TSOPS/W Digital Neuromorphic Processor With Unified SNN-ANN and On-Chip Learning Paradigm. - Yi Zhong; Yisong Kuang; Kefei Liu 002; Zilin Wang 001; Shuo Feng; Guang Chen; Youming Yang 002; Xiuping Cui; Qiankun Wang; Jian Cao 002; Song Jia; Yun Liang 001; et al. (IEEE J. Solid State Circuits, 2025)