Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit. - Charles Tsen; Michael J. Schulte; Sonia González-Navarro (ASAP, 2007)

Hardware design of a Binary Integer Decimal-based floating-point adder. - Charles Tsen; Sonia González-Navarro; Michael J. Schulte (ICCD, 2007)

A Combined Decimal and Binary Floating-Point Multiplier. - Charles Tsen; Sonia González-Navarro; Michael J. Schulte; Brian J. Hickmann; Katherine Compton (ASAP, 2009)

Analytical Model of Patching and Load Sharing in a Distributed VoD System. - Sonia González-Navarro; Juan López; Angeles G. Navarro; Emilio L. Zapata (PDPTA, 2009)

Hardware Designs for Binary Integer Decimal-Based Rounding. - Samuel Tsen; Sonia González-Navarro; Michael J. Schulte; Katherine Compton (IEEE Trans. Computers, 2011)

Decimal online multioperand addition. - Carlos Garcia-Vega; Sonia González-Navarro; Julio Villalba; Emilio L. Zapata (ACSCC, 2012)

On-line Decimal Adder with RBCD Representation. - Carlos Garcia-Vega; Sonia González-Navarro; Julio Villalba-Moreno; Emilio L. Zapata (ASAP, 2012)

A study of decimal left shifters for binary numbers. - Sonia González-Navarro; Javier Hormigo; Michael J. Schulte (Inf. Comput., 2012)

Binary Integer Decimal-Based Floating-Point Multiplication. - Sonia González-Navarro; Charles Tsen; Michael J. Schulte (IEEE Trans. Computers, 2013)

Decimal Multiformat Online Addition. - Carlos Garcia-Vega; Sonia González-Navarro; Pedro Balboa-La Chica; Julio Villalba-Moreno (IEEE Trans. Computers, 2016)

Normalizing or Not Normalizing? An Open Question for Floating-Point Arithmetic in Embedded Systems. - Sonia González-Navarro; Javier Hormigo (ARITH, 2017)

Unbiased Rounding for HUB Floating-Point Addition. - Julio Villalba-Moreno; Javier Hormigo; Sonia González-Navarro (IEEE Trans. Computers, 2018)

Boosting Backward Search Throughput for FM-Index Using a Compressed Encoding. - Jose Manuel Herruzo; Sonia González-Navarro; Pablo Ibáñez 001; Víctor Viñals; Jesús Alastruey-Benedé; Oscar G. Plata (DCC, 2019)

Fast HUB Floating-Point Adder for FPGA. - Julio Villalba; Javier Hormigo; Sonia González-Navarro (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

Floating-Point Fused Multiply-Add under HUB Format. - Javier Hormigo; Julio Villalba-Moreno; Sonia Gonzalez-Navarro (ARITH, 2020)

New Results on Non-Normalized Floating-Point Formats. - Sonia González-Navarro; Javier Hormigo (IEEE Trans. Computers, 2020)

Accelerating Sequence Alignments Based on FM-Index Using the Intel KNL Processor. - Jose Manuel Herruzo; Sonia González-Navarro; Pablo Ibáñez-Marín; Víctor Viñals Yúfera; Jesús Alastruey-Benedé; Oscar G. Plata (IEEE ACM Trans. Comput. Biol. Bioinform., 2020)

Genome Sequence Alignment - Design Space Exploration for Optimal Performance and Energy Architectures. - Yasir Mahmood Qureshi; Jose Manuel Herruzo; Marina Zapater; Katzalin Olcoz; Sonia Gonzalez-Navarro; Oscar G. Plata; David Atienza (IEEE Trans. Computers, 2021)

Enabling fast and energy-efficient FM-index exact matching using processing-near-memory. - Jose Manuel Herruzo; Ivan Fernandez; Sonia González-Navarro; Oscar G. Plata (J. Supercomput., 2021)

TraTSA: A Transprecision Framework for Efficient Time Series Analysis. - Ivan Fernandez; Ricardo Quislant; Sonia Gonzalez-Navarro; Eladio Gutiérrez; Oscar G. Plata (J. Comput. Sci., 2022)