A 283.2μW 800Mb/s/pin DLL-based data self-aligner for Through-Silicon Via (TSV) interface. - Hyun-Woo Lee; Soo-Bin Lim; Junyoung Song; Jabeom Koo; Dae-Han Kwon; Jong-Ho Kang; Yunsaing Kim; Young-Jung Choi; Kunwoo Park; Byong-Tae Chung; Chulwoo Kim (ISSCC, 2012)

An adaptive-bandwidth PLL for avoiding noise interference and DFE-less fast precharge sampling for over 10Gb/s/pin graphics DRAM interface. - Junyoung Song; Hyun-Woo Lee; Soo-Bin Lim; Sewook Hwang; Yunsaing Kim; Young-Jung Choi; Byong-Tae Chung; Chulwoo Kim (ISSCC, 2013)

A 247 µW 800 Mb/s/pin DLL-Based Data Self-Aligner for Through Silicon via (TSV) Interface. - Soo-Bin Lim; Hyun-Woo Lee; Junyoung Song; Chulwoo Kim (IEEE J. Solid State Circuits, 2013)

A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications. - Kyu-Dong Hwang; Boram Kim; Sang-Yeon Byeon; Kyu-Young Kim; Dae-Han Kwon; Hyun-Bae Lee; Geun-Il Lee; Sang-Sic Yoon; Jin-Youp Cha; Soo-Young Jang; Seung-Hun Lee; Yongsuk Joo; et al. (ISSCC, 2018)