Full chip integration of 3-d cross-point ReRAM with leakage-compensating write driver and disturbance-aware sense amplifier. - Sangheon Lee; Jeonghwan Song; Changhyuk Seong; Jiyong Woo; Jong-Moon Choi; Soon-Chan Kwon; Ho-Joon Kim; Hyun-Suk Kang; Soo Gil Kim; Hoe Gwon Jung; Kee-Won Kwon; Hyunsang Hwang (VLSI Circuits, 2016)

Fabrication and Characterization of a Fully Si Compatible Forming-Free GeOxResistive Switching Random-Access Memory. - Jae Yoon Lee; Youngmin Kim; Ikhyeon Kworn; Il Hwan Cho; Jae Yeon Lee; Soo Gil Kim; Seongjae Cho (DRC, 2018)

Realistic Noise-aware Training as a Component of the Holistic ACiM Development Platform. - Jihun Kim; Sangsu Park; Hongju Suh; Youngjae Kwon; Seonghun Lee; Yubin Lee; Kayoung Kim; Eungu Han; Jongil Kim; Kyu Sung Kim; Hyejung Choi; Seungwook Ryu; et al. (IMW, 2024)

Improvement of MAC Accuracy using Oxygen Diffusion Barriers in Resistive Synaptic Cell Arrays. - Youngjae Kwon; Won-Tae Koo; Sangsu Park; Dong Ik Suh; Gunhee Lee; Hyung Dong Lee; Youngbae Ahn; Dohee Kim; Seungwook Ryu; Hoseok Em; Seokjoon Kang; Chang Won Jeong; et al. (IMW, 2024)

30.6 A 64Gb DDR4 STT-MRAM Using a Time-Controlled Discharge-Reading Scheme for a .001681µm 1T-1MTJ Cross-Point Cell. - Kosuke Hatsuda; Katsuhiko Hoya; Ryosuke Takizawa; Fumiyoshi Matsuoka; Takaya Yasuda; Akira Katayama; Tadashi Miyakawa; Kazuyo Senju; Kazuki Okawa; Yuka Furukawa; Yu Shimada; Katsuya Kotake; et al. (ISSCC, 2025)