Content-addressable memory for VLSI pattern inspection. - Soo-Ik Chae; James T. Walker; Chong-Cheng Fu; R. Fabian Pease (IEEE J. Solid State Circuits, 1988)

Modified Probabilistic RAM Archticture for VLSI Implementation of a Backpropagation Learning Algorithm. - Eel-Wan Lee; Jae-Hee Won; Soo-Ik Chae (ISCAS, 1993)

Character Recognition by Neural Networks with Single-Layer Training and Rejection Mechanism. - Joonho Lim; Eel-Wan Lee; Soo-Ik Chae (ISCAS, 1994)

A Study on the Stochastic Computation Using the Ratio of One Pulses and Zero Pulses. - Seung-Jai Min; Eel-Wan Lee; Soo-Ik Chae (ISCAS, 1994)

Stereo Correspondence with Discrete-Time Cellular Neural Networks. - Sungjun Park; Seung-Jai Min; Soo-Ik Chae (ISCAS, 1994)

New classifier with reduced computational complexity. - Eel-Wan Lee; Soo-Ik Chae (ICNN, 1995)

Ratio pulse arithmetic for radial basis function network. - Joonho Lim; Soo-Ik Chae (ICNN, 1995)

Corrective training of hidden control neural network. - KyungMin Na; Soo-Ik Chae; SouGuil Ann (ICNN, 1995)

Discriminative training of hidden Markov models using overall risk criterion and reduced gradient method. - Kyungmin Na; Bumki Jeon; Dong-Il Chang; Soo-Ik Chae; Souguil Ann (EUROSPEECH, 1995)

Recurrent neural prediction models for speech recognition. - Kyungmin Na; Jekwan Ryu; Dong-Il Chang; Soo-Ik Chae; Souguil Ann (EUROSPEECH, 1995)

New Perceptron Model Using Random Bitstreams. - Eel-Wan Lee; Soo-Ik Chae (Neural Comput., 1995)

GPD training of the state weighting functions in hidden control neural network. - Kyungmin Na; Soo-Ik Chae (ICASSP, 1996)

Fast vector quantizer using multiple sorted index tables. - Sun-Young Choi; Soo-Ik Chae (ICIP (3), 1996)

Two-step motion estimation algorithm using low-resolution quantization. - Seongsoo Lee; Soo-Ik Chae (ICIP (3), 1996)

Single-sensor active noise cancellation using recurrent neural network predictors. - Kyungmin Na; Soo-Ik Chae (ICNN, 1997)

Improved sufficient convergence condition for the discrete-time cellular neural networks. - Sungjun Park; Soo-Ik Chae (ICNN, 1997)

Digital implementation of discrete-time cellular neural networks with distributed arithmetic. - Sungjun Park; Joonho Lim; Soo-Ik Chae (ICNN, 1997)

Partial bus-invert coding for power optimization of system level bus. - Youngsoo Shin; Soo-Ik Chae; Kiyoung Choi (ISLPED, 1998)

Fast Design of Reduced-Complexity Nearest-Neighbor Classifiers Using Triangular Inequality. - Eel-Wan Lee; Soo-Ik Chae (IEEE Trans. Pattern Anal. Mach. Intell., 1998)

New motion estimation algorithm using adaptively quantized low bit-resolution image and its VLSI architecture for MPEG2 video encoding. - Seongsoo Lee; Jeong-Min Kim; Soo-Ik Chae (IEEE Trans. Circuits Syst. Video Technol., 1998)

A 16-bit carry-lookahead adder using reversible energy recovery logic for ultra-low-energy systems. - Joonho Lim; Dong-Gyu Kim; Soo-Ik Chae (IEEE J. Solid State Circuits, 1999)

An 8×8 nRERL serial multiplier for ultra-low-power aplications. - Joonho Lim; Dong-Gyu Kim; Sang-Chul Kang; Soo-Ik Chae (ASP-DAC, 2000)

Frequency-domain separation of convolved non-stationary signals with adaptive non-causal FIR filters. - Kyungmin Na; Kyung Jin Lee; Soo-Ik Chae (EUSIPCO, 2000)

A three-port nRERL register file for ultra-low-energy applications. - Jun-Ho Kwon; Joonho Lim; Soo-Ik Chae (ISLPED, 2000)

Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). - Koichi Nose; Soo-Ik Chae; Takayasu Sakurai (ISLPED, 2000)

Emulator Environment Based on an FPGA Prototyping Board. - Kyung-soo Oh; Sang-yong Yoon; Soo-Ik Chae (IEEE International Workshop on Rapid System Prototyping, 2000)

nMOS reversible energy recovery logic for ultra-low-energy applications. - Joonho Lim; Dong-Gyu Kim; Soo-Ik Chae (IEEE J. Solid State Circuits, 2000)

An 8-b nRERL microprocessor for ultra-low-energy applications. - Seokkee Kim; Jun-Ho Kwon; Soo-Ik Chae (ASP-DAC, 2001)

Partial bus-invert coding for power optimization of application-specific systems. - Youngsoo Shin; Soo-Ik Chae; Kiyoung Choi (IEEE Trans. Very Large Scale Integr. Syst., 2001)

A cycle-accurate joulemeter for CMOS VLSI circuits. - Eunseok Song; In-Chan Choi; Young-Kil Park; Soo-Ik Chae (ESSCIRC, 2003)

An Efficient Simulation Environment and Simulation Techniques for Bluetooth Device Design. - Yongjin Ahn; Daehong Kim; Sunghyun Lee; Sanggyu Park; Sungjoo Yoo; Kiyoung Choi; Soo-Ik Chae (Des. Autom. Embed. Syst., 2003)

An efficient scalable and flexible data transfer architecture for multiprocessor SoC with massive distributed memory. - Sang-Il Han; Amer Baghdadi; Marius Bonaciu; Soo-Ik Chae; Ahmed Amine Jerraya (DAC, 2004)

A Cycle-Accurate Energy Estimator for CMOS Digital Circuits. - Eunseok Song; Young-Kil Park; Soon Kwon; Soo-Ik Chae (PATMOS, 2004)

A 2.4-GHz 0.25-μm CMOS dual-mode direct-conversion transceiver for bluetooth and 802.11b. - Yeon-Jae Jung; Hoesam Jeong; Eunseok Song; Jungho Lee; Seung-Wook Lee; Donghyeon Seo; Inho Song; Sanghun Jung; Joonbae Park; Deog-Kyoon Jeong; Soo-Ik Chae; W. Kim (IEEE J. Solid State Circuits, 2004)

A reset-free anti-harmonic delay-locked loop using a cycle period detector. - Eunseok Song; Seung-Wook Lee; Jeong-Woo Lee; Joonbae Park; Soo-Ik Chae (IEEE J. Solid State Circuits, 2004)

A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC/H.264. - Minho Kim; Ingu Hwang; Soo-Ik Chae (ASP-DAC, 2005)

Implementation of a simple 8-bit microprocessor with reversible energy recovery logic. - Seokkee Kim; Soo-Ik Chae (Conf. Computing Frontiers, 2005)

Complexity reduction in an nRERL microprocessor. - Seokkee Kim; Soo-Ik Chae (ISLPED, 2005)

A Two-Week Program for a Platform-Based SoC Design. - Sanggyu Park; Soo-Ik Chae (MSE, 2005)

A C/C++-Based Functional Verification Framework Using the SystemC Verification Library. - Sanggyu Park; Soo-Ik Chae (IEEE International Workshop on Rapid System Prototyping, 2005)

A 0.25-μm CMOS quad-band GSM RF transceiver using an efficient LO frequency plan. - Eunseok Song; Yido Koo; Yeon-Jae Jung; Deok-Hee Lee; Sangyoung Chu; Soo-Ik Chae (IEEE J. Solid State Circuits, 2005)

Implementation of an OpenVG Rasterizer with Configurable Anti-Aliasing and Multi-Window Scissoring. - Ren Huang; Soo-Ik Chae (CIT, 2006)

Functional modeling techniques for efficient SW code generation of video codec applications. - Sang-Il Han; Soo-Ik Chae; Ahmed Amine Jerraya (ASP-DAC, 2006)

Reusable component IP design using refinement-based design environment. - Sanggyu Park; Sang-yong Yoon; Soo-Ik Chae (ASP-DAC, 2006)

Buffer memory optimization for video codec application modeled in Simulink. - Sang-Il Han; Xavier Guerin; Soo-Ik Chae; Ahmed Amine Jerraya (DAC, 2006)

A Mixed-Level Virtual Prototyping Environment for Refinement-Based Design Environment. - Sanggyu Park; Sang-yong Yoon; Soo-Ik Chae (IEEE International Workshop on Rapid System Prototyping, 2006)

A Bootstrapped Switch for nMOS Reversible Energy Recovery Logic for Low-Voltage Applications. - Seokkee Kim; Soo-Ik Chae (IEICE Trans. Electron., 2006)

Simulink-Based MPSoC Design Flow: Case Study of Motion-JPEG and H.264. - Kai Huang 002; Sang-Il Han; Katalin Popovici; Lisane B. de Brisolara; Xavier Guerin; Lei Li; Xiaolang Yan; Soo-Ik Chae; Luigi Carro; Ahmed Amine Jerraya (DAC, 2007)

Reducing fine-grain communication overhead in multithread code generation for heterogeneous MPSoC. - Lisane B. de Brisolara; Sang-Il Han; Xavier Guerin; Luigi Carro; Ricardo Reis 001; Soo-Ik Chae; Ahmed Amine Jerraya (SCOPES, 2007)

Memory-efficient multithreaded code generation from Simulink for heterogeneous MPSoC. - Sang-Il Han; Soo-Ik Chae; Lisane B. de Brisolara; Luigi Carro; Ricardo Reis 001; Xavier Guerin; Ahmed Amine Jerraya (Des. Autom. Embed. Syst., 2007)

RTL Generation of Channel Architecture Templates for a Template-based SoC Design Flow. - Jinhyun Cho; Soonwoo Choi; Soo-Ik Chae (FDL, 2008)

A hardware operating system kernel for multi-processor systems. - Sanggyu Park; Do-sun Hong; Soo-Ik Chae (IEICE Electron. Express, 2008)

Cache Optimization for H.264/AVC Motion Compensation. - Sang-yong Yoon; Soo-Ik Chae (IEICE Trans. Inf. Syst., 2008)

A high-performance OpenVG accelerator with dual-scanline filling rendering. - Daewoong Kim; Kilhyung Cha; Soo-Ik Chae (IEEE Trans. Consumer Electron., 2008)

Configurable high-performance video platform using multiple RISC clusters connected with separated data and control networks. - Daewoong Kim; Kilhyung Cha; Soonwoo Choi; Soo-Ik Chae (SiPS, 2009)

VLSI Implementation of a VC-1 Main Profile Decoder for HD Video Applications. - Jinhyun Cho; Doowon Lee; Sang-yong Yoon; Sanggyu Park; Soo-Ik Chae (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Adaptive Scanline Filling Algorithm for OpenVG 2D Vector Graphics Accelerator. - Daewoong Kim; Kilhyung Cha; Soo-Ik Chae (IEICE Trans. Inf. Syst., 2009)

Simulink®-based heterogeneous multiprocessor SoC design flow for mixed hardware/software refinement and simulation. - Sang-Il Han; Soo-Ik Chae; Lisane B. de Brisolara; Luigi Carro; Katalin Popovici; Xavier Guerin; Ahmed Amine Jerraya; Kai Huang 002; Lei Li; Xiaolang Yan (Integr., 2009)

A mixed-level virtual prototyping environment for SystemC-based design methodology. - Sanggyu Park; Sang-yong Yoon; Soo-Ik Chae (Microelectron. J., 2009)

A 40 Mbps H.264/AVC CAVLC decoder using a 64-bit multiple-issue video parsing coprocessor. - Soonwoo Choi; Jason Jong Kyu Park; Moonmo Koo; Daewoong Kim; Soo-Ik Chae (SoCC, 2010)

Flexible DMA subsystem in multi-core platforms for video applications. - Moonmo Koo; Soo-Ik Chae (IEICE Electron. Express, 2010)

Constrained-random bitstream generation for H.264/AVC decoder conformance test. - Jinhyun Cho; Soonwoo Choi; Soo-Ik Chae (IEEE Trans. Consumer Electron., 2010)

A Programmable Video Platform and Its Application Mapping Framework Using the Target Application's SystemC Models. - Daewoong Kim; Kilhyung Cha; Doo-Seung Hong; Soonwoo Choi; Soo-Ik Chae (EURASIP J. Embed. Syst., 2011)

Generation of efficient bitstreams for functional tests of video decoders. - Soonwoo Choi; Seunggyu Jeoung; Jicheon Kim; Soo-Ik Chae (ICCE, 2013)

Next-Generation Memory [Guest editors' introduction]. - Greg Atwood; Soo-Ik Chae; Simon S. Y. Shim (Computer, 2013)

Efficient test bitstream generation with an N-way covering algorithm for configurations of high-level syntax elements in video decoders. - Soonwoo Choi; Jicheon Kim; Soo-Ik Chae (IEEE Trans. Consumer Electron., 2013)

Coding efficiency of the context-based arithmetic coding engine of AVS 2.0 in the HEVC encoder. - Hyunmin Jung; Soonwoo Choi; Soo-Ik Chae (ICCE, 2015)

Coding efficiency of AVS 2.0 for CBAC and CABAC engines. - Jing Cui; Youngkyu Choi; Soo-Ik Chae (ICMV, 2015)

Decoding of main 4: 2: 2 10-bit bitstreams in HEVC Main 8-bit best-effort decoders. - Woo Seok Jeong; Hyunmin Jung; Soo-Ik Chae (ICCE, 2016)

Fast Integer Motion Estimation With Bottom-Up Motion Vector Prediction for an HEVC Encoder. - Tae Sung Kim; Chae-Eun Rhee; Hyuk-Jae Lee; Soo-Ik Chae (IEEE Trans. Circuits Syst. Video Technol., 2018)

An adaptive hash-based search for integer motion estimation in SCC. - Youngkyu Choi; Hyuk-Jae Lee; Soo-Ik Chae (IEICE Electron. Express, 2019)

High Throughput CBAC Hardware Encoder With Bin Merging for AVS 2.0 Video Coding. - Youngkyu Choi; Hyuk-Jae Lee; Soo-Ik Chae (IEEE Trans. Circuits Syst. Video Technol., 2021)