An experimental 16-Mbit DRAM with reduced peak-current noise. - Daeje Chin; Changhyun Kim; Yunho Choi; Dong-Sun Min; Hong-Sun Hwang; Hoon Choi; Soo-In Cho; Tae-Young Chung; Chan J. Park; Yunseung Shin; Kwang Pyuk Suh; Yong E. Park (IEEE J. Solid State Circuits, 1989)

Temperature-compensation circuit techniques for high-density CMOS DRAMs. - Dong-Sun Min; Soo-In Cho; Dong Soo Jun; Dong-Jae Lee; Yongsik Seok; Daeje Chin (IEEE J. Solid State Circuits, 1992)

Variable VCC design techniques for battery-operated DRAMs. - Seung-Moon Yoo; Ejaz Haq; Seung-Hoon Lee; Yun-Ho Choi; Soo-In Cho; Nam-Soo Kang; Daeje Chin (IEEE J. Solid State Circuits, 1993)

16-Mb synchronous DRAM with 125-Mbyte/s data rate. - Yunho Choi; Myungho Kim; Hyunsoon Jang; Taejin Kim; Seung-hoon Lee; Ho-cheol Lee; Churoo Park; Siyeol Lee; Cheol-soo Kim; Soo-In Cho; Ejaz Haq; J. Karp; et al. (IEEE J. Solid State Circuits, 1994)

A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth. - Jei-Hwan Yoo; Chang-Hyun Kim; Kyu-Chan Lee; Kye-Hyun Kyung; Seung-Moon Yoo; Jung-Hwa Lee; Moon-Hae Son; Jin-Man Han; Bok-Moon Kang; Ejaz Haq; Sang-Bo Lee; Jai-Hoon Sim; et al. (IEEE J. Solid State Circuits, 1996)

Low-voltage, high-speed circuit designs for gigabit DRAMs. - Kyu-Chan Lee; Changhyun Kim; Dong-Ryul Ryu; Jai-Hoon Sim; Sang-Bo Lee; Byung-Sik Moon; Keum-Yong Kim; Nam-Jong Kim; Seung-Moon Yoo; Hongil Yoon; Jei-Hwan Yoo; Soo-In Cho (IEEE J. Solid State Circuits, 1997)

A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system. - Chang-Hyun Kim; Jung-Hwa Lee; J. B. Lee; Beomsup Kim; C. S. Park; Sang-Bo Lee; S. Y. Lee; C. W. Park; J. G. Roh; Hyoung Sik Nam; D. Y. Kim; D. Y. Lee; et al. (IEEE J. Solid State Circuits, 1998)

A 1 Gbit synchronous dynamic random access memory with an independent subarray-controlled scheme and a hierarchical decoding scheme. - Kyu-Chan Lee; Changhyun Kim; Hongil Yoon; Keum-Yong Kim; Byung-Sik Moon; Sang-Bo Lee; Jung-Hwa Lee; Nam-Jong Kim; Soo-In Cho (IEEE J. Solid State Circuits, 1998)

A 2.5-V, 72-Mbit, 2.0-GByte/s packet-based DRAM with a 1.0-Gbps/pin interface. - Changhyun Kim; Kye-Hyun Kyung; W.-P. Jeong; J.-S. Kim; Byung-Sik Moon; Joon-Wan Chai; S.-M. Yim; Jung-Hwan Choi; K.-H. Han; C.-J. Park; Hong-Sun Hwang; H. Choi; et al. (IEEE J. Solid State Circuits, 1999)

A 1-Gb/s bidirectional I/O buffer using the current-mode scheme. - Jae-Yoon Sim; Young-Soo Sohn; Seung-Chan Heo; Hong-June Park; Soo-In Cho (IEEE J. Solid State Circuits, 1999)

A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM. - Hongil Yoon; Gi-Won Cha; Changsik Yoo; Nam-Jong Kim; Keum-Yong Kim; Chang Ho Lee; Kyu-Nam Lim; Kyuchan Lee; Jun-Young Jeon; Tae Sung Jung; Hongsik Jeong; Tae-Young Chung; et al. (IEEE J. Solid State Circuits, 1999)

A low-jitter mixed-mode DLL for high-speed DRAM applications. - Jae Joon Kim; Sang-Bo Lee; Tae-Sung Jung; Chang-Hyun Kim; Soo-In Cho; Beomsup Kim (IEEE J. Solid State Circuits, 2000)

A dual-loop delay-locked loop using multiple voltage-controlled delay lines. - Yeon-Jae Jung; Seung-Wook Lee; Daeyun Shim; Wonchan Kim; Changhyun Kim; Soo-In Cho (IEEE J. Solid State Circuits, 2001)

A 2.5-V 2.0-Gbyte/s 288-Mb packet-based DRAM with enhanced cell efficiency and noise immunity. - Kyehyun Kyung; Hi-Choon Lee; Ki-Whan Song; Ho-Sung Song; Keewook Jung; Joon-Seo Moon; Byoung-Sul Kim; Sung-Burn Cho; Changhyun Kim; Soo-In Cho (IEEE J. Solid State Circuits, 2001)

A CMOS transceiver for DRAM bus system with a demultiplexed equalization scheme. - Jae-Yoon Sim; Jang-Jin Nam; Young-Soo Sohn; Hong-June Park; Chang-Hyun Kim; Soo-In Cho (IEEE J. Solid State Circuits, 2002)

A 2.2 Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation. - Young-Soo Sohn; Seung-Jun Bae; Hong-June Park; Changhyun Kim; Soo-In Cho (CICC, 2003)

A 1.8-V 128-Mb mobile DRAM with double boosting pump, hybrid current sense amplifier, and dual-referenced adjustment scheme for temperature sensor. - Jae-Yoon Sim; Hongil Yoon; Ki-Chul Chun; Hyun-Seok Lee; Sang-Pyo Hong; Kyu-Chan Lee; Jei-Hwan Yoo; Dong-Il Seo; Soo-In Cho (IEEE J. Solid State Circuits, 2003)

A 3.6-Gb/s point-to-point heterogeneous-voltage-capable DRAM interface for capacity-scalable memory subsystems. - Joseph T. Kennedy; Randy Mooney; Robert Ellis; James E. Jaussi; Shekhar Borkar; Jung-Hwan Choi; Jae-Kwan Kim 003; Chan-Kyong Kim; Woo-Seop Kim; Chang-Hyun Kim; Soo-In Cho; Steffen Loeffler; et al. (IEEE J. Solid State Circuits, 2005)

A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control. - Sang-Bo Lee; Seong-Jin Jang; Jin-Seok Kwak; Sang-Jun Hwang; Young-Hyun Jun; Soo-In Cho; Chil-Gee Lee (IEEE J. Solid State Circuits, 2005)

A 512-mb DDR3 SDRAM prototype with CIO minimization and self-calibration techniques. - Churoo Park; Hoeju Chung; Yun-Sang Lee; Jaekwan Kim 003; JaeJun Lee; Moo Sung Chae; Dae-Hee Jung; Sung-Ho Choi; Seung-young Seo; Taek-Seon Park; Jun-Ho Shin; Jin-Hyung Cho; et al. (IEEE J. Solid State Circuits, 2006)

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion. - Jeong-Don Ihm; Seung-Jun Bae; Kwang-Il Park; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Ho-Kyung Lee; Min-Sang Park; Sam-Young Bang; Mi-Jin Lee; Gil-Shin Moon; et al. (ISSCC, 2007)

A DLL with Jitter-Reduction Techniques for DRAM Interfaces. - Byung-Guk Kim; Lee-Sup Kim; Kwang-Il Park; Young-Hyun Jun; Soo-In Cho (ISSCC, 2007)

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion. - Seung-Jun Bae; Kwang-Il Park; Jeong-Don Ihm; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Yoon-Sik Park; Min-Sang Park; Hong-Kyong Lee; Sam-Young Bang; Gil-Shin Moon; et al. (IEEE J. Solid State Circuits, 2008)

A DLL With Jitter Reduction Techniques and Quadrature Phase Generation for DRAM Interfaces. - Byung-Guk Kim; Lee-Sup Kim; Kwang-Il Park; Young-Hyun Jun; Soo-In Cho (IEEE J. Solid State Circuits, 2009)